CY7C2568KV18-400BZXC

CY7C2568KV18-400BZXC Datasheet

CY7C2566KV18, CY7C2577KV18

Part	Datasheet
CY7C2568KV18-400BZXC	CY7C2568KV18-400BZXC (pdf)

Related Parts	Information
CY7C2568KV18-450BZC	CY7C2568KV18-450BZC
CY7C2570KV18-400BZC	CY7C2570KV18-400BZC
CY7C2570KV18-450BZC	CY7C2570KV18-450BZC
CY7C2568KV18-400BZC	CY7C2568KV18-400BZC
CY7C2568KV18-500BZC	CY7C2568KV18-500BZC
CY7C2570KV18-500BZC	CY7C2570KV18-500BZC

PDF Datasheet Preview
CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT 72-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT Configurations • 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 550 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double data rate DDR interfaces  data transferred at 1100 MHz at 550 MHz • Available in clock cycle latency • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo Clocks CQ and CQ simplify data capture in high speed systems • Data valid pin QVLD to indicate valid data on the output • On-die termination ODT feature Supported for D[x:0], BWS[x:0], and K/K inputs • Synchronous internally self-timed writes • DDR II+ operates with cycle read latency when DOFF is asserted HIGH • Operates similar to DDR I Device with 1 cycle read latency when DOFF is asserted LOW • Core VDD = 1.8V ± 0.1V I/O VDDQ = 1.4V to VDD[1] Supports both 1.5V and 1.8V I/O supply • HSTL inputs and variable drive HSTL output buffers • Available in 165-Ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Phase-locked loop PLL for accurate data placement With Read Cycle Latency of cycles: CY7C2566KV18 8M x 8 CY7C2577KV18 8M x 9 CY7C2568KV18 4M x 18 CY7C2570KV18 2M x 36 Functional Description The CY7C2566KV18, CY7C2577KV18, CY7C2568KV18, and CY7C2570KV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C2566KV18 , 9-bit words CY7C2577KV18 , 18-bit words CY7C2568KV18 , or 36-bit words CY7C2570KV18 that burst sequentially into or out of the device. These devices have an On-Die Termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Table Selection Guide Description Maximum Operating Frequency Maximum Operating Current 550 MHz 500 MHz 500 690 700 890 450 MHz 450 630 650 820 400 MHz 400 580 590 750 Unit MHz mA Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD. Test Data-Out TDO 13 Performing a TAP Reset 13 TAP Registers 13 TAP Instruction Set 13 TAP Controller State Diagram 15 TAP Controller Block Diagram 16 TAP Electrical Characteristics 16 TAP AC Switching Characteristics 17 TAP Timing and Test Conditions 17 Power Up Sequence in DDR II+ SRAM 20 Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 DC Electrical Characteristics 21 AC Electrical Characteristics 22 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence 25 Ordering Information 26 Package Diagram 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29 Page 4 of 29 [+] Feedback CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18 Pin Configuration The pin configuration for CY7C2566KV18, CY7C2577KV18, CY7C2568KV18, and CY7C2570KV18 follow. [2] 165-Ball FBGA 13 x 15 x mm Pinout CY7C2566KV18 8M x 8 NWS1 K NC/144M LD A NC/288M K NWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ QVLD 11 CQ DQ3 NC DQ2 NC ZQ NC DQ0 NC TDI CY7C2577KV18 8M x 9 K NC/144M LD A NC/288M K BWS0 VDDQ VDDQ VDDQ VDDQ VDDQ Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 500 CY7C2568KV18-500BZC CY7C2570KV18-500BZC 450 CY7C2568KV18-450BZC CY7C2570KV18-450BZC 400 CY7C2568KV18-400BZC CY7C2570KV18-400BZC CY7C2568KV18-400BZXC Package Diagram Part and Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Operating Range Commercial 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Page 26 of 29 [+] Feedback Package Diagram Figure 165-Ball FBGA 13 x 15 x mm TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18 BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180-C Page 27 of 29 [+] Feedback CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18 Document History Page Document Title 72-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT Document Number 001-15889 ECN No. Converted from preliminary to final For 550 MHz, 500 MHz and 450 MHz bins, changed tCO, tCCQO, tCHZ specs to 450 ps and tDOH, tCQOH, tCLZ to -450 ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information F 2762555 NJY 09/11/2009 Updated Input and Output Capacitance. Modified Ordering code disclaimer. G 2794726 VKN 10/29/09 Included CY7C2568KV18-400BZXC in the Ordering Information table Updated 165-ball package diagram Added the page H 2896003 NJY 03/19/10 Removed inactive parts from Ordering Information. Updated package diagram. Updated links in Sales, Solutions, and Legal Information. I 2931775 VKN 05/13/10 Included following parts in the Ordering information table CY7C2568KV18-550BZC, and CY7C2570KV18-550BZC. J 2972174 NJY 07/08/10 Corrected title in first page of the document. *K 3056613 BDK 10/12/10 Removed forecasted parts - CY7C2570KV18-550BZC, CY7C2568KV18-550BZC. Added Ordering Code Definitions. Page 28 of 29 [+] Feedback CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 29 of 29 [+] Feedback

PDF Datasheet Preview

CY7C2566KV18, CY7C2577KV18

CY7C2568KV18, CY7C2570KV18
72-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT
72-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT

Configurations
• 72-Mbit density 8M x 8, 8M x 9, 4M x 18, 2M x 36
• 550 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate DDR interfaces  data transferred at 1100 MHz at 550 MHz
• Available in clock cycle latency
• Two input clocks K and K for precise DDR timing SRAM uses rising edges only
• Echo Clocks CQ and CQ simplify data capture in high speed systems
• Data valid pin QVLD to indicate valid data on the output
• On-die termination ODT feature Supported for D[x:0], BWS[x:0], and K/K inputs
• Synchronous internally self-timed writes
• DDR II+ operates with cycle read latency when DOFF is asserted HIGH
• Operates similar to DDR I Device with 1 cycle read latency when DOFF is asserted LOW
• Core VDD = 1.8V ± 0.1V I/O VDDQ = 1.4V to VDD[1] Supports both 1.5V and 1.8V I/O supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-Ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Phase-locked loop PLL for accurate data placement

With Read Cycle Latency of cycles:

CY7C2566KV18 8M x 8

CY7C2577KV18 8M x 9

CY7C2568KV18 4M x 18

CY7C2570KV18 2M x 36

Functional Description

The CY7C2566KV18, CY7C2577KV18, CY7C2568KV18, and CY7C2570KV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C2566KV18 , 9-bit words CY7C2577KV18 , 18-bit words CY7C2568KV18 , or 36-bit words CY7C2570KV18 that burst sequentially into or out of the device.

These devices have an On-Die Termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing.

Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Table Selection Guide Description

Maximum Operating Frequency Maximum Operating Current
550 MHz
500 MHz 500 690 700 890
450 MHz 450 630 650 820
400 MHz 400 580 590 750

Unit MHz mA

Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
Test Data-Out TDO 13 Performing a TAP Reset 13 TAP Registers 13 TAP Instruction Set 13 TAP Controller State Diagram 15 TAP Controller Block Diagram 16 TAP Electrical Characteristics 16 TAP AC Switching Characteristics 17 TAP Timing and Test Conditions 17 Power Up Sequence in DDR II+ SRAM 20 Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 DC Electrical Characteristics 21 AC Electrical Characteristics 22 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence 25 Ordering Information 26 Package Diagram 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29

Page 4 of 29 [+] Feedback

CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18

Pin Configuration

The pin configuration for CY7C2566KV18, CY7C2577KV18, CY7C2568KV18, and CY7C2570KV18 follow. [2]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C2566KV18 8M x 8

NWS1

K NC/144M LD

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

QVLD
11 CQ DQ3 NC DQ2 NC ZQ NC DQ0 NC TDI

CY7C2577KV18 8M x 9

K NC/144M LD

A NC/288M K

BWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
500 CY7C2568KV18-500BZC

CY7C2570KV18-500BZC
450 CY7C2568KV18-450BZC

CY7C2570KV18-450BZC
400 CY7C2568KV18-400BZC

CY7C2570KV18-400BZC

CY7C2568KV18-400BZXC

Package Diagram

Part and Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

Page 26 of 29 [+] Feedback

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180-*C

Page 27 of 29 [+] Feedback

CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18

Document History Page

Document Title 72-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency with ODT Document Number 001-15889

ECN No.
Converted from preliminary to final For 550 MHz, 500 MHz and 450 MHz bins, changed tCO, tCCQO, tCHZ specs to 450 ps and tDOH, tCQOH, tCLZ to -450 ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information
*F 2762555 NJY
09/11/2009 Updated Input and Output Capacitance. Modified Ordering code disclaimer.
*G 2794726 VKN
10/29/09
Included CY7C2568KV18-400BZXC in the Ordering Information table Updated 165-ball package diagram Added the page
*H 2896003 NJY
03/19/10
Removed inactive parts from Ordering Information. Updated package diagram. Updated links in Sales, Solutions, and Legal Information.
*I 2931775 VKN
05/13/10 Included following parts in the Ordering information table CY7C2568KV18-550BZC, and CY7C2570KV18-550BZC.
*J 2972174 NJY
07/08/10 Corrected title in first page of the document.
*K 3056613 BDK
10/12/10 Removed forecasted parts - CY7C2570KV18-550BZC, CY7C2568KV18-550BZC. Added Ordering Code Definitions.

Page 28 of 29 [+] Feedback

CY7C2566KV18, CY7C2577KV18 CY7C2568KV18, CY7C2570KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 29 of 29
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C2568KV18-400BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C2568KV18-400BZXC 508091