CY7C185-20PC

CY7C185-20PC Datasheet

CY7C185

Part	Datasheet
CY7C185-20PC	CY7C185-20PC (pdf)

Related Parts	Information
CY7C185-25VC	CY7C185-25VC
CY7C185-25PC	CY7C185-25PC
CY7C185-35PC	CY7C185-35PC

PDF Datasheet Preview
CY7C185 8K x 8 Static RAM • High speed 15 ns • Fast tDOE • Low active power 715 mW • Low standby power 220 mW • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected Functional Description[1] The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is Logic Block Diagram A1 A2 A3 A4 A5 A6 A7 A8 CE1 CE2 WE OE INPUT BUFFER 256 x 32 x 8 ARRAY POWER COLUMN DECODER DOWN provided by an active LOW chip enable CE1 , an active HIGH chip enable CE2 , and active LOW output enable OE and three-state drivers. This device has an automatic power-down feature CE1 or CE2 , reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package. An active LOW write enable signal WE controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins I/O0 through I/O7 is written into the memory location addressed by the address present on the address pins A0 through A12 . Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable WE is HIGH. A die coat is used to insure alpha immunity. Pin Configurations DIP/SOJ/SOIC Top View I/O0 I/O1 I/O2 I/O3 A7 5 A8 6 A9 7 A10 8 A11 9 A12 10 I/O0 11 I/O1 12 I/O2 13 GND 14 28 VCC 27 WE 26 CE2 25 A3 24 A2 23 A1 22 OE 21 A0 20 CE1 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 I/O4 I/O5 I/O6 I/O7 ROW DECODER A0 A9 A10 A11 A12 SENSE AMPS Selection Guide[2] 7C185-15 7C185-20 7C185-25 7C185-35 Maximum Access Time ns Maximum Operating Current mA Maximum Standby Current mA Ordering Information Speed ns 15 Ordering Code CY7C185-15PC CY7C185-15SC CY7C185-15VC CY7C185-15VI CY7C185-20PC CY7C185-20SC CY7C185-20VC CY7C185-20VI 25 CY7C185-25PC CY7C185-25SC CY7C185-25VC CY7C185-25VI 35 CY7C185-35PC CY7C185-35SC CY7C185-35VC CY7C185-35VI Package Name P21 S21 V21 P21 S21 V21 P21 S21 V21 P21 S21 V21 Package Type 28-Lead 300-Mil Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead 300-Mil Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead 300-Mil Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead 300-Mil Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Page 8 of 11 Package Diagrams 28-Lead 300-Mil Molded DIP P21 CY7C185 28-Lead 300-Mil Molded SOIC S21 51-85014-B 51-85026-A Page 9 of 11 Package Diagrams continued 28-Lead 300-Mil Molded SOJ V21 CY7C185 51-85031-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Page 10 of 11 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Document History Page Document Title CY7C185 8K x 8 Static RAM Document Number 38-05043 Issue ECN NO. Date Orig. of Change 107145 09/10/01 116470 09/16/02 Description of Change from Spec number 38-00037 to 38-05043 Add applications foot note to data sheet. CY7C185 Page 11 of 11

PDF Datasheet Preview

CY7C185
8K x 8 Static RAM
• High speed 15 ns
• Fast tDOE
• Low active power
715 mW
• Low standby power
220 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected

Functional Description[1]

The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is

Logic Block Diagram

A1 A2 A3 A4 A5 A6 A7 A8

CE1 CE2 WE OE

INPUT BUFFER
256 x 32 x 8 ARRAY

POWER

COLUMN DECODER DOWN
provided by an active LOW chip enable CE1 , an active HIGH chip enable CE2 , and active LOW output enable OE and three-state drivers. This device has an automatic power-down feature CE1 or CE2 , reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package.

An active LOW write enable signal WE controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins I/O0 through I/O7 is written into the memory location addressed by the address present on the address pins A0 through A12 . Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable WE is HIGH. A die coat is used to insure alpha immunity.

Pin Configurations

DIP/SOJ/SOIC Top View

I/O0 I/O1 I/O2 I/O3

A7 5 A8 6 A9 7 A10 8 A11 9 A12 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC
27 WE
26 CE2
25 A3
24 A2 23 A1 22 OE 21 A0 20 CE1 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3

I/O4

I/O5

I/O6

I/O7

ROW DECODER A0 A9 A10 A11 A12

SENSE AMPS

Selection Guide[2]
7C185-15
7C185-20
7C185-25
7C185-35

Maximum Access Time ns

Maximum Operating Current mA

Maximum Standby Current mA
Ordering Information

Speed ns 15
Ordering Code CY7C185-15PC CY7C185-15SC CY7C185-15VC CY7C185-15VI CY7C185-20PC CY7C185-20SC CY7C185-20VC CY7C185-20VI
25 CY7C185-25PC CY7C185-25SC CY7C185-25VC CY7C185-25VI
35 CY7C185-35PC CY7C185-35SC CY7C185-35VC CY7C185-35VI

Package Name P21 S21 V21 P21 S21 V21 P21 S21 V21 P21 S21 V21

Package Type 28-Lead 300-Mil Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead 300-Mil Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead 300-Mil Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ 28-Lead 300-Mil Molded DIP 28-Lead Molded SOIC 28-Lead Molded SOJ 28-Lead Molded SOJ

Operating Range

Commercial

Industrial Commercial

Industrial Commercial

Industrial Commercial

Industrial

Page 8 of 11

Package Diagrams
28-Lead 300-Mil Molded DIP P21

CY7C185
28-Lead 300-Mil Molded SOIC S21
51-85014-*B
51-85026-*A

Page 9 of 11

Package Diagrams continued
28-Lead 300-Mil Molded SOJ V21

CY7C185
51-85031-*B

All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 10 of 11

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Document History Page

Document Title CY7C185 8K x 8 Static RAM Document Number 38-05043

Issue ECN NO. Date

Orig. of Change
107145 09/10/01
116470 09/16/02

Description of Change from Spec number 38-00037 to 38-05043 Add applications foot note to data sheet.

CY7C185

Page 11 of 11

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C185-20PC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C185-20PC 508074