CY7C1563V18-375BZC

CY7C1563V18-375BZC Datasheet


CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

Part Datasheet
CY7C1563V18-375BZC CY7C1563V18-375BZC CY7C1563V18-375BZC (pdf)
Related Parts Information
CY7C1563V18-400BZC CY7C1563V18-400BZC CY7C1563V18-400BZC
CY7C1565V18-400BZC CY7C1565V18-400BZC CY7C1565V18-400BZC
CY7C1565V18-400BZXC CY7C1565V18-400BZXC CY7C1565V18-400BZXC
CY7C1565V18-400BZI CY7C1565V18-400BZI CY7C1565V18-400BZI
CY7C1565V18-375BZC CY7C1565V18-375BZC CY7C1565V18-375BZC
CY7C1563V18-400BZXC CY7C1563V18-400BZXC CY7C1563V18-400BZXC
PDF Datasheet Preview
CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18
72-Mbit QDR -II+ SRAM 4-Word Burst Architecture Cycle Read Latency
• Separate independent read and write data ports Supports concurrent transactions
• 400 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double Data Rate DDR interfaces on both read and write ports
data transferred at 800 MHz at 400 MHz
• Available in clock cycle latency
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high-speed
systems
• Data valid pin QVLD to indicate valid data on the output
• Single multiplexed address input bus latches address inputs
for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V ± 0.1V IO VDDQ = 1.4V to VDD [1]
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-Ball FBGA package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

With Read Cycle Latency of cycles:

CY7C1561V18 8M x 8

CY7C1576V18 8M x 9

CY7C1563V18 4M x 18

CY7C1565V18 2M x 36

Functional Description

The CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II+ architecture. Similar to QDR-II architecture, QDR-II+ SRAMs consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR-II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words CY7C1561V18 , 9-bit words CY7C1576V18 , 18-bit words CY7C1563V18 , or 36-bit words CY7C1565V18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
400 MHz
1400
1400
1400
1400
375 MHz 375 1300
333 MHz 333 1200
300 MHz 300 1100

Unit MHz mA

Note The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

VDDQ = 1.4V to VDD.
• San Jose, CA 95134-1709
• 408-943-2600
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Logic Block Diagram CY7C1561V18

CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18

D[7:0]

A 20:0 21

Address Register

K DOFF

VREF WPS NWS[1:0]

CLK Gen.
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
400 CY7C1561V18-400BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1576V18-400BZC

CY7C1563V18-400BZC

CY7C1565V18-400BZC

CY7C1561V18-400BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1576V18-400BZXC

CY7C1563V18-400BZXC

CY7C1565V18-400BZXC

CY7C1561V18-400BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1576V18-400BZI

CY7C1563V18-400BZI

CY7C1565V18-400BZI

CY7C1561V18-400BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1576V18-400BZXI

CY7C1563V18-400BZXI

CY7C1565V18-400BZXI
375 CY7C1561V18-375BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1576V18-375BZC

CY7C1563V18-375BZC

CY7C1565V18-375BZC

CY7C1561V18-375BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1576V18-375BZXC

CY7C1563V18-375BZXC

CY7C1565V18-375BZXC

CY7C1561V18-375BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1576V18-375BZI
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
333 CY7C1561V18-333BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1576V18-333BZC

CY7C1563V18-333BZC

CY7C1565V18-333BZC

CY7C1561V18-333BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1576V18-333BZXC

CY7C1563V18-333BZXC

CY7C1565V18-333BZXC

CY7C1561V18-333BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1576V18-333BZI

CY7C1563V18-333BZI

CY7C1565V18-333BZI

CY7C1561V18-333BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1576V18-333BZXI

CY7C1563V18-333BZXI

CY7C1565V18-333BZXI
300 CY7C1561V18-300BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1576V18-300BZC

CY7C1563V18-300BZC

CY7C1565V18-300BZC

CY7C1561V18-300BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1576V18-300BZXC

CY7C1563V18-300BZXC

CY7C1565V18-300BZXC

CY7C1561V18-300BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1576V18-300BZI
*E 1351243 See ECN VKN/FSU Converted from preliminary to final Added x8 and x9 parts Changed tCYC max spec to ns for all speed bins Updated footnote# 23 Updated Ordering Information table
*F 2181046 See ECN VKN/AESA Added footnote# 22 related to IDD

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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Datasheet ID: CY7C1563V18-375BZC 508070