CY7C1523JV18-300BZXC

CY7C1523JV18-300BZXC Datasheet

CY7C1522JV18, CY7C1529JV18 CY7C1523JV18, CY7C1524JV18

Part	Datasheet
CY7C1523JV18-300BZXC	CY7C1523JV18-300BZXC (pdf)

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CY7C1522JV18, CY7C1529JV18 CY7C1523JV18, CY7C1524JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture • 72 Mbit Density 8M x 8, 8M x 9, 4M x 18, 2M x 36 • 300 MHz Clock for High Bandwidth • 2-word Burst for reducing Address Bus Frequency • Double Data Rate DDR Interfaces data transferred at 600 MHz at 300 MHz • Two Input Clocks K and K for precise DDR timing SRAM uses rising edges only • Two Input Clocks for output data C and C to minimize Clock Skew and Flight Time mismatches • Echo Clocks CQ and CQ Simplify Data Capture in High Speed Systems • Synchronous Internally Self-timed Writes • DDR-II operates with Cycle Read Latency when the Delay Lock Loop DLL is enabled • Operates similar to a DDR-I device with 1 Cycle Read Latency in DLL Off Mode • 1.8V Core Power Supply with HSTL inputs and outputs • Variable drive HSTL Output Buffers • Expanded HSTL Output Voltage • Available in 165-Ball FBGA Package 15 x 17 x mm • Offered in both Pb-free and non Pb-free packages • JTAG Compatible Test Access Port • Delay Lock Loop DLL for Accurate Data Placement Configurations CY7C1522JV18 8M x 8 CY7C1529JV18 8M x 9 CY7C1523JV18 4M x 18 CY7C1524JV18 2M x 36 Selection Guide Maximum Operating Frequency Maximum Operating Current Functional Description The CY7C1522JV18, CY7C1529JV18, CY7C1523JV18, and CY7C1524JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O DDR-II SIO architecture. The DDR-II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1522JV18, two 9-bit words in the case of CY7C1529JV18, two 18-bit words in the case of CY7C1523JV18, and two 36-bit words in the case of CY7C1524JV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. 300 MHz 300 900 950 1080 250 MHz 250 800 900 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1522JV18, CY7C1529JV18 CY7C1523JV18, CY7C1524JV18 Logic Block Diagram CY7C1522JV18 8 D[7:0] A 21:0 22 Address Register K DOFF CLK Gen. R/W VREF NWS[1:0] Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 300 CY7C1522JV18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1529JV18-300BZC CY7C1523JV18-300BZC CY7C1524JV18-300BZC CY7C1522JV18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1529JV18-300BZXC CY7C1523JV18-300BZXC CY7C1524JV18-300BZXC CY7C1522JV18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1529JV18-300BZI CY7C1523JV18-300BZI CY7C1524JV18-300BZI CY7C1522JV18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1529JV18-300BZXI CY7C1523JV18-300BZXI CY7C1524JV18-300BZXI 250 CY7C1522JV18-250BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1529JV18-250BZC CY7C1523JV18-250BZC CY7C1524JV18-250BZC CY7C1522JV18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1529JV18-250BZXC CY7C1523JV18-250BZXC CY7C1524JV18-250BZXC CY7C1522JV18-250BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1529JV18-250BZI

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CY7C1522JV18, CY7C1529JV18 CY7C1523JV18, CY7C1524JV18
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
• 72 Mbit Density 8M x 8, 8M x 9, 4M x 18, 2M x 36
• 300 MHz Clock for High Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate DDR Interfaces data transferred at 600 MHz at 300 MHz
• Two Input Clocks K and K for precise DDR timing SRAM uses rising edges only
• Two Input Clocks for output data C and C to minimize Clock Skew and Flight Time mismatches
• Echo Clocks CQ and CQ Simplify Data Capture in High Speed Systems
• Synchronous Internally Self-timed Writes
• DDR-II operates with Cycle Read Latency when the Delay Lock Loop DLL is enabled
• Operates similar to a DDR-I device with 1 Cycle Read Latency in DLL Off Mode
• 1.8V Core Power Supply with HSTL inputs and outputs
• Variable drive HSTL Output Buffers
• Expanded HSTL Output Voltage
• Available in 165-Ball FBGA Package 15 x 17 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG Compatible Test Access Port
• Delay Lock Loop DLL for Accurate Data Placement

Configurations

CY7C1522JV18 8M x 8 CY7C1529JV18 8M x 9 CY7C1523JV18 4M x 18 CY7C1524JV18 2M x 36

Selection Guide

Maximum Operating Frequency

Maximum Operating Current

Functional Description

The CY7C1522JV18, CY7C1529JV18, CY7C1523JV18, and CY7C1524JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O DDR-II SIO architecture. The DDR-II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1522JV18, two 9-bit words in the case of CY7C1529JV18, two 18-bit words in the case of CY7C1523JV18, and two 36-bit words in the case of CY7C1524JV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
300 MHz 300 900 950 1080
250 MHz 250 800 900

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1522JV18, CY7C1529JV18 CY7C1523JV18, CY7C1524JV18

Logic Block Diagram CY7C1522JV18
8 D[7:0]

A 21:0 22

Address Register

K DOFF

CLK Gen.

R/W VREF

NWS[1:0]
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
300 CY7C1522JV18-300BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1529JV18-300BZC

CY7C1523JV18-300BZC

CY7C1524JV18-300BZC

CY7C1522JV18-300BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1529JV18-300BZXC

CY7C1523JV18-300BZXC

CY7C1524JV18-300BZXC

CY7C1522JV18-300BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1529JV18-300BZI

CY7C1523JV18-300BZI

CY7C1524JV18-300BZI

CY7C1522JV18-300BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1529JV18-300BZXI

CY7C1523JV18-300BZXI

CY7C1524JV18-300BZXI
250 CY7C1522JV18-250BZC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1529JV18-250BZC

CY7C1523JV18-250BZC

CY7C1524JV18-250BZC

CY7C1522JV18-250BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free

CY7C1529JV18-250BZXC

CY7C1523JV18-250BZXC

CY7C1524JV18-250BZXC

CY7C1522JV18-250BZI
51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1529JV18-250BZI

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Datasheet ID: CY7C1523JV18-300BZXC 508066