CY7C1514KV18-200BZXC

CY7C1514KV18-200BZXC Datasheet

CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18

Part	Datasheet
CY7C1514KV18-200BZXC	CY7C1514KV18-200BZXC (pdf)

Related Parts	Information
CY7C1512KV18-200BZXC	CY7C1512KV18-200BZXC

PDF Datasheet Preview
CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit II SRAM 2-Word Burst Architecture Configurations • Separate Independent Read and Write Data Ports Supports concurrent transactions • 350 MHz Clock for High Bandwidth • 2-word Burst on all Accesses • Double Data Rate DDR Interfaces on both Read and Write Ports data transferred at 700 MHz at 350 MHz • Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only • Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches • Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems • Single Multiplexed Address Input bus latches Address Inputs for both Read and Write Ports • Separate Port Selects for Depth Expansion • Synchronous internally Self-timed Writes • II operates with Cycle Read Latency when DOFF is asserted HIGH • Operates similar to QDR I Device with 1 Cycle Read Latency when DOFF is asserted LOW • Available in x8, x9, x18, and x36 Configurations • Full Data Coherency, providing Most Current Data • Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD Supports both 1.5V and 1.8V I/O supply • Available in 165-ball FBGA Package 13 x 15 x mm • Offered in both Pb-free and non Pb-free Packages • Variable Drive HSTL Output Buffers • JTAG Compatible Test Access Port • Phase Locked Loop PLL for Accurate Data Placement CY7C1510KV18 8M x 8 CY7C1525KV18 8M x 9 CY7C1512KV18 4M x 18 CY7C1514KV18 2M x 36 Functional Description The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words CY7C1510KV18 , 9-bit words CY7C1525KV18 , 18-bit words CY7C1512KV18 , or 36-bit words CY7C1514KV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Table Selection Guide Description Maximum Operating Frequency Maximum Operating Current 350 MHz 350 x8 825 x9 825 x18 840 x36 1030 333 MHz 333 790 810 990 300 MHz 300 730 750 910 250 MHz 250 640 650 790 200 MHz 200 540 550 660 167 MHz 167 480 490 580 Unit MHz mA Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 DC Electrical Characteristics 21 AC Electrical Characteristics 23 Capacitance 24 Thermal Resistance 24 Switching Characteristics 25 Switching Waveforms 27 Ordering Information 28 Package Diagram 29 Document History Page 30 Sales, Solutions, and Legal Information 31 Worldwide Sales and Design Support 31 Products 31 Page 4 of 31 [+] Feedback CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Pin Configuration The pin configurations for CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 follow.[1] 165-Ball FBGA 13 x 15 x mm Pinout CY7C1510KV18 8M x 8 WPS NWS1 K NC/144M RPS A NC/288M K NWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CY7C1525KV18 8M x 9 K NC/144M RPS A NC/288M K BWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 350 CY7C1512KV18-350BZC 333 CY7C1525KV18-333BZC CY7C1512KV18-333BZC CY7C1514KV18-333BZC CY7C1525KV18-333BZXC CY7C1512KV18-333BZXC CY7C1514KV18-333BZXC CY7C1512KV18-333BZI CY7C1514KV18-333BZI CY7C1512KV18-333BZXI CY7C1514KV18-333BZXI 300 CY7C1525KV18-300BZC CY7C1512KV18-300BZC CY7C1514KV18-300BZC CY7C1525KV18-300BZXC CY7C1512KV18-300BZXC CY7C1514KV18-300BZXC CY7C1512KV18-300BZI CY7C1514KV18-300BZI CY7C1512KV18-300BZXI CY7C1514KV18-300BZXI 250 CY7C1525KV18-250BZC CY7C1512KV18-250BZC CY7C1514KV18-250BZC CY7C1525KV18-250BZXC CY7C1512KV18-250BZXC CY7C1514KV18-250BZXC CY7C1512KV18-250BZI CY7C1514KV18-250BZI CY7C1525KV18-250BZXI CY7C1512KV18-250BZXI CY7C1514KV18-250BZXI Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Operating Range Commercial Commercial 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Table Ordering Information continued Speed MHz Ordering Code 200 CY7C1525KV18-200BZC CY7C1512KV18-200BZC CY7C1514KV18-200BZC CY7C1525KV18-200BZXC CY7C1512KV18-200BZXC CY7C1514KV18-200BZXC CY7C1512KV18-200BZI CY7C1514KV18-200BZI CY7C1512KV18-200BZXI CY7C1514KV18-200BZXI Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Operating Range Commercial 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180-C Page 29 of 31 [+] Feedback CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Document History Page Document Title 72-Mbit II SRAM 2-Word Burst Architecture Document Number 001-00436 ECN No. See ECN Updated IDD Spec Updated ordering information table B 1699083 VKN/AESA See ECN Converted from Advance Information to Preliminary C 2148307 VKN/AESA See ECN Changed PLL lock time from 1024 cycles to 20 us Added footnote #19 related to IDD Corrected typo in the footnote #23 D 2606839 VKN/PYRS 11/13/08 Changed JTAG ID [31:29] from 001 to 000, Updated power up sequence waveform and its description, Changed Ambient Temperature with Power Applied from “-10°C to +85°C” to “-55°C to +125°C” in the “Maximum Ratings” on page 20, Included Thermal Resistance values, Changed the package size from 15 x 17 x mm to 13 x 15 x mm. E 2681899 VKN/PYRS 04/01/2009 Converted from preliminary to final Added note on top of the Ordering Information table Moved to external web F 2747635 VKN/AESA 08/03/2009 Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information G 2767155 09/23/2009 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer H 2794726 VKN 10/29/09 Included CY7C1525KV18-250BZXI in the Ordering Information table Updated 165-ball package diagram Added the Contents page I 2868256 01/28/2010 Included 350 MHz speed information Included CY7C1512KV18-350BZC in the Ordering Information table J 2870201 02/01/2010 No technical updates. Post to external web. Page 30 of 31 [+] Feedback CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 31 of 31 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18
72-Mbit II SRAM 2-Word Burst Architecture

Configurations
• Separate Independent Read and Write Data Ports Supports concurrent transactions
• 350 MHz Clock for High Bandwidth
• 2-word Burst on all Accesses
• Double Data Rate DDR Interfaces on both Read and Write Ports data transferred at 700 MHz at 350 MHz
• Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only
• Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches
• Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems
• Single Multiplexed Address Input bus latches Address Inputs for both Read and Write Ports
• Separate Port Selects for Depth Expansion
• Synchronous internally Self-timed Writes
• II operates with Cycle Read Latency when DOFF is
asserted HIGH
• Operates similar to QDR I Device with 1 Cycle Read Latency when DOFF is asserted LOW
• Available in x8, x9, x18, and x36 Configurations
• Full Data Coherency, providing Most Current Data
• Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD Supports both 1.5V and 1.8V I/O supply
• Available in 165-ball FBGA Package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free Packages
• Variable Drive HSTL Output Buffers
• JTAG Compatible Test Access Port
• Phase Locked Loop PLL for Accurate Data Placement

CY7C1510KV18 8M x 8

CY7C1525KV18 8M x 9

CY7C1512KV18 4M x 18

CY7C1514KV18 2M x 36

Functional Description

The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 8-bit words CY7C1510KV18 , 9-bit words CY7C1525KV18 , 18-bit words CY7C1512KV18 , or 36-bit words CY7C1514KV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Table Selection Guide Description

Maximum Operating Frequency Maximum Operating Current
350 MHz 350
x8 825 x9 825 x18 840 x36 1030
333 MHz 333 790 810 990
300 MHz 300 730 750 910
250 MHz 250 640 650 790
200 MHz 200 540 550 660
167 MHz 167 480 490 580

Unit MHz mA
Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 DC Electrical Characteristics 21 AC Electrical Characteristics 23 Capacitance 24 Thermal Resistance 24 Switching Characteristics 25 Switching Waveforms 27 Ordering Information 28 Package Diagram 29 Document History Page 30 Sales, Solutions, and Legal Information 31 Worldwide Sales and Design Support 31 Products 31

Page 4 of 31 [+] Feedback

CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18

Pin Configuration

The pin configurations for CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 follow.[1]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C1510KV18 8M x 8

WPS NWS1

K NC/144M RPS

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

CY7C1525KV18 8M x 9

K NC/144M RPS

A NC/288M K

BWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
350 CY7C1512KV18-350BZC
333 CY7C1525KV18-333BZC

CY7C1512KV18-333BZC

CY7C1514KV18-333BZC

CY7C1525KV18-333BZXC

CY7C1512KV18-333BZXC

CY7C1514KV18-333BZXC

CY7C1512KV18-333BZI

CY7C1514KV18-333BZI

CY7C1512KV18-333BZXI

CY7C1514KV18-333BZXI
300 CY7C1525KV18-300BZC

CY7C1512KV18-300BZC

CY7C1514KV18-300BZC

CY7C1525KV18-300BZXC

CY7C1512KV18-300BZXC

CY7C1514KV18-300BZXC

CY7C1512KV18-300BZI

CY7C1514KV18-300BZI

CY7C1512KV18-300BZXI

CY7C1514KV18-300BZXI
250 CY7C1525KV18-250BZC

CY7C1512KV18-250BZC

CY7C1514KV18-250BZC

CY7C1525KV18-250BZXC

CY7C1512KV18-250BZXC

CY7C1514KV18-250BZXC

CY7C1512KV18-250BZI

CY7C1514KV18-250BZI

CY7C1525KV18-250BZXI

CY7C1512KV18-250BZXI

CY7C1514KV18-250BZXI

Package Diagram

Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial

Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free
Table Ordering Information continued

Speed MHz
Ordering Code
200 CY7C1525KV18-200BZC

CY7C1512KV18-200BZC

CY7C1514KV18-200BZC

CY7C1525KV18-200BZXC

CY7C1512KV18-200BZXC

CY7C1514KV18-200BZXC

CY7C1512KV18-200BZI

CY7C1514KV18-200BZI

CY7C1512KV18-200BZXI

CY7C1514KV18-200BZXI

Package Diagram

Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180-*C

Page 29 of 31 [+] Feedback

CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18

Document History Page

Document Title 72-Mbit II SRAM 2-Word Burst Architecture Document Number 001-00436

ECN No.
See ECN Updated IDD Spec Updated ordering information table
*B 1699083 VKN/AESA See ECN Converted from Advance Information to Preliminary
*C 2148307 VKN/AESA See ECN Changed PLL lock time from 1024 cycles to 20 us Added footnote #19 related to IDD Corrected typo in the footnote #23
*D 2606839 VKN/PYRS 11/13/08 Changed JTAG ID [31:29] from 001 to 000, Updated power up sequence waveform and its description, Changed Ambient Temperature with Power Applied from “-10°C to +85°C” to “-55°C to +125°C” in the “Maximum Ratings” on page 20, Included Thermal Resistance values, Changed the package size from 15 x 17 x mm to 13 x 15 x mm.
*E 2681899 VKN/PYRS 04/01/2009 Converted from preliminary to final Added note on top of the Ordering Information table Moved to external web
*F 2747635 VKN/AESA 08/03/2009 Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information
*G 2767155
09/23/2009 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer
*H 2794726 VKN
10/29/09 Included CY7C1525KV18-250BZXI in the Ordering Information table Updated 165-ball package diagram Added the Contents page
*I 2868256
01/28/2010 Included 350 MHz speed information Included CY7C1512KV18-350BZC in the Ordering Information table
*J 2870201
02/01/2010 No technical updates. Post to external web.

Page 30 of 31 [+] Feedback

CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 31 of 31

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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Datasheet ID: CY7C1514KV18-200BZXC 508059