CY7C1470V33-167BZXI
CY7C1470V33-167BZXI Datasheet
CY7C1470V33 CY7C1472V33 CY7C1474V33
| Part | Datasheet |
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CY7C1470V33-167BZXI |
CY7C1470V33-167BZXI (pdf) |
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CY7C1470V33-167BZXC |
CY7C1470V33-167BZXC |
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| CY7C1470V33 CY7C1472V33 CY7C1474V33 72 Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture • Pin compatible and functionally equivalent to ZBT • Supports 250 MHz Bus Operations with Zero Wait States Available speed grades are 250, 200 and 167 MHz • Internally self timed Output Buffer Control to eliminate the need to use asynchronous OE • Fully registered inputs and outputs for Pipelined Operation • Byte Write Capability • Single 3.3V Power Supply • 3.3V/2.5V I/O Power Supply • Fast Clock-to-output time ns for 250 MHz device • Clock Enable CEN pin to suspend operation • Synchronous Self Timed Writes • CY7C1470V33, CY7C1472V33 available in JEDEC-standard Pb-Free 100-pin TQFP, Pb-Free and non-Pb-Free 165-ball FBGA package. CY7C1474V33 available in Pb-Free and non-Pb-Free 209 ball FBGA package • IEEE JTAG Boundary Scan compatible • Burst or Interleaved Burst Order • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects for CY7C1474V33, for CY7C1470V33 and for CY7C1472V33 and a Write Enable WE input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tristate control. In order to avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Logic Block Diagram CY7C1470V33 2M x 36 A0, A1, A MODE ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 ADV/LD BW a BW b BW c BW d WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S E D A T A S T E R I N Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code Package Diagram Part and Package Type 167 CY7C1470V33-167AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free CY7C1470V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1470V33-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Pb-Free CY7C1474V33-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1470V33-167AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free CY7C1472V33-167AXI CY7C1470V33-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm CY7C1470V33-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Pb-Free 200 CY7C1470V33-200AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free CY7C1472V33-200AXC CY7C1474V33-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1470V33-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x 1.4mm Operating Range Commercial lndustrial Commercial lndustrial Page 24 of 30 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Package Diagrams Figure 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm 100 1 81 80 R MIN. MAX. GAUGE PLANE 0° -7° REF. 30 31 0° MIN. R MIN. MAX. MIN. DETAIL A TYP. 51 50 12° ±1° 8X SEE DETAIL MAX. MAX. STAND-OFF MIN. MAX. SEATING PLANE NOTE JEDEC STD REF MS-026 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED in mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH DIMENSIONS IN MILLIMETERS 51-85050 *B Page 25 of 30 [+] Feedback Package Diagrams continued Figure 165-ball FBGA 15 x 17 x mm Updated ordering information Changed Advanced Information to Preliminary 223721 See ECN Changed timing diagrams Changed logic block diagrams Modified Functional Description Modified “Functional Overview” section Added boundary scan order for all packages Included thermal numbers and capacitance values for all packages Included IDD and ISB values Removed 250 MHz offering and included 225 MHz speed bin Changed package outline for 165FBGA package and 209-ball BGA package Removed 119-BGA package offering 235012 See ECN Minor Change The data sheets do not match on the spec system and external web 243572 See ECN Changed ball C11,D11,E11,F11,G11 from DQPb,DQb,DQb,DQb,DQb to DQPa,DQa,DQa,DQa,DQa in page 4 Modified capacitance values in page 20 299511 See ECN Removed 225 MHz offering and included 250 MHz speed bin Changed tCYC from ns to ns for 250 MHz Speed Bin Changed ΘJA from to °C/W and ΘJC from to °C/W for 100 TQFP Package on Page # 20 Added Pb-Free information for 100-Pin TQFP and 165 FBGA Packages Added comment of ‘Pb-Free BG packages availability’ below the Ordering Information Add Industrial part numbers in Ordering Info section 323039 See ECN Unshaded 250 MHz speed bin in the AC/DC Table and Selection Guide Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Modified VOL, VOH Test Conditions Changed package name from 209-ball PBGA to 209-ball FBGA on page# 5 Removed comment of ‘Pb-Free BG packages availability below the Ordering Information Updated Ordering Information Table Changed from Preliminary to Final 351937 See ECN Updated Ordering Information Table Page 28 of 30 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Document Title CY7C1470V33/CY7C1472V33/CY7C1474V33, 72 Mbit 2M x 36/4M x 18/1M x 72 Pipelined SRAM with NoBL Architecture Document Number 38-05289 Orig. of Submission Change Description of Change 416221 See ECN Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-state to Tristate Changed the description of IX from Input Load Current to Input Leakage Current on page# 18 Changed the IX current values of MODE on page # 18 from uA and 30 uA to uA and 5 uA Changed the IX current values of ZZ on page # 18 from uA and 5 uA to uA and 30 uA Changed VDDQ < VDD to VDDQ < VDD in page #18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated the Ordering Information Table 472335 See ECN Corrected the typo in the pin configuration for 209-Ball FBGA pinout Corrected the ball name for H9 to VSS from VSSQ . Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. 2756998 08/28/09 Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Updated Package Diagram for spec Page 29 of 30 [+] Feedback CY7C1470V33 CY7C1472V33 CY7C1474V33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 30 of 30 NoBLTM and No Bus LatencyTM are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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