CY7C1464AV33-167BGI

CY7C1464AV33-167BGI Datasheet

CY7C1460AV33 CY7C1462AV33 CY7C1464AV33

Part	Datasheet
CY7C1464AV33-167BGI	CY7C1464AV33-167BGI (pdf)

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CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture • Pin compatible and functionally equivalent to ZBT • Supports 250 MHz Bus Operations with Zero Wait States Available speed grades are 250, 200 and 167 MHz • Internally self timed Output Buffer Control to eliminate the need to use Asynchronous OE • Fully registered inputs and outputs for Pipelined Operation • Byte Write Capability • 3.3V Power Supply • 3.3V/2.5V I/O Power Supply • Fast Clock-to-output times ns for 250 MHz device • Clock Enable CEN Pin to suspend operation • Synchronous self timed Writes • CY7C1460AV33, CY7C1462AV33 available in JEDEC-standard Pb-Free 100-pin TQFP, Pb-Free and non-Pb-Free 165-ball FBGA package. CY7C1464AV33 available in Pb-Free and non-Pb-Free 209-ball FBGA package • IEEE JTAG-Compatible Boundary Scan • Burst or Interleaved Burst Order • “ZZ” Sleep Mode Option and Stop Clock Option Functional Description The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV33/ CY7C1462AV33/CY7C1464AV33 are equipped with the advanced NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects for CY7C1464AV33, for CY7C1460AV33 and for CY7C1462AV33 and a Write Enable WE input. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. Logic Block Diagram CY7C1460AV33 1M x 36 A0, A1, A MODE ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 ADV/LD BW a BW b BW c BW d WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S E D A T A S T E R I N DC Electrical Characteristics Over the Operating Range 19 Capacitance 20 Thermal Resistance 20 Switching Characteristics Over the Operating Range 21 Ordering 25 Package 25 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support....................... 29 Products 29 PSoC Solutions 29 Page 3 of 28 [+] Feedback Pin Configurations Figure 100-Pin TQFP Pinout CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 100 A 99 A 98 CE1 97 CE2 96 BWd 95 BWc 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A 100 A 99 A 98 CE1 97 CE2 96 NC 95 NC 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A DQPc 1 DQc 2 DQc 3 VDDQ 4 VSS 5 DQc 6 DQc 7 DQc 8 DQc 9 VDDQ 11 DQc 12 DQc 13 NC 14 VDD 15 VSS 17 DQd 18 DQd 19 VDDQ 20 VSS 21 DQd 22 DQd 23 DQd 24 DQd 25 VSS 26 VDDQ 27 DQd 28 DQd 29 DQPd 30 CY7C1460AV33 1M x 36 80 DQPb NC 1 79 DQb NC 2 78 DQb NC 3 77 VDDQ 4 76 VSS VSS 5 75 DQb NC 6 74 DQb NC 7 73 DQb 8 72 DQb 9 71 70 VDDQ 10 11 69 DQb 12 68 DQb 13 67 VSS NC 66 NC 65 VDD NC Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 167 CY7C1460AV33-167AXC CY7C1462AV33-167AXC CY7C1460AV33-167BZC CY7C1460AV33-167AXI CY7C1464AV33-167BGI 200 CY7C1460AV33-200AXC 250 CY7C1460AV33-250AXC CY7C1460AV33-250BZC CY7C1460AV33-250AXI Package Diagram Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free Operating Range Commercial Industrial Commercial Industrial Package Diagrams Figure 100-Pin TQFP 14 x 20 x mm 51-85050 C Page 24 of 28 [+] Feedback Package Diagrams continued Figure 165-Ball FBGA 15 x 17 x mm CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 51-85165 B Page 25 of 28 [+] Feedback Package Diagrams continued Figure 209-Ball FBGA 14 x 22 x mm CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 51-85167 A Page 26 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Document History Page Document Title CY7C1460AV33/CY7C1462AV33/CY7C1464AV33, 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Document Number 38-05353 Orig. of Change Submission Date Description of Change 254911 See ECN New Data sheet Updated the Ordering Information by Shading and Unshading MPNs as per availability 417509 See ECN Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed IX current value in MODE from and 30 uA to and 5 uA respectively and also Changed IX current value in ZZ from and 5 uA to and 30 uA respectively on page# 18 Modified test condition from VIH < VDD to VIH < VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from A to *B 473229 See ECN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table. Page 27 of 28 [+] Feedback CY7C1460AV33 CY7C1462AV33 CY7C1464AV33 Document Title CY7C1460AV33/CY7C1462AV33/CY7C1464AV33, 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Document Number 38-05353 2756998 08/28/09 Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering infor- mation. Updated Package Diagram for spec 2900822 03/29/2010 Added CY7C1460AV33-167AXI part in Ordering Information Updated links in Sales, Solutions, and Legal Information Updated 100-pin TQFP and 209-Ball FBGA package diagrams. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 28 of 28 is the registered trademark and NoBLTM and No Bus LatencyTM are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture
• Pin compatible and functionally equivalent to ZBT
• Supports 250 MHz Bus Operations with Zero Wait States Available speed grades are 250, 200 and 167 MHz
• Internally self timed Output Buffer Control to eliminate the need to use Asynchronous OE
• Fully registered inputs and outputs for Pipelined Operation
• Byte Write Capability
• 3.3V Power Supply
• 3.3V/2.5V I/O Power Supply
• Fast Clock-to-output times ns for 250 MHz device
• Clock Enable CEN Pin to suspend operation
• Synchronous self timed Writes
• CY7C1460AV33, CY7C1462AV33 available in JEDEC-standard Pb-Free 100-pin TQFP, Pb-Free and non-Pb-Free 165-ball FBGA package. CY7C1464AV33 available in Pb-Free and non-Pb-Free 209-ball FBGA package
• IEEE JTAG-Compatible Boundary Scan
• Burst or Interleaved Burst Order
• “ZZ” Sleep Mode Option and Stop Clock Option

Functional Description

The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V, 1M x 36/2M x 18/512K x72 Synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV33/ CY7C1462AV33/CY7C1464AV33 are equipped with the advanced NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects for CY7C1464AV33, for CY7C1460AV33 and for CY7C1462AV33 and a Write Enable WE input. All writes are conducted with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence.

Logic Block Diagram CY7C1460AV33 1M x 36

A0, A1, A

MODE

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

ADV/LD

BW a BW b BW c BW d

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

WRITE DRIVERS

MEMORY ARRAY

S E N S E A M P S

O U T P U T R E G I S T E R S E

D A T A S T E R I N
DC Electrical Characteristics Over the Operating Range 19 Capacitance 20 Thermal Resistance 20 Switching Characteristics Over the Operating Range 21 Ordering 25 Package 25 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support....................... 29 Products 29 PSoC Solutions 29

Page 3 of 28 [+] Feedback

Pin Configurations

Figure 100-Pin TQFP Pinout

CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
100 A 99 A 98 CE1 97 CE2 96 BWd 95 BWc 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A 100 A 99 A 98 CE1 97 CE2 96 NC 95 NC 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A

DQPc 1

DQc 2

DQc 3 VDDQ 4

VSS 5 DQc 6

DQc 7

DQc 8

DQc 9

VDDQ 11

DQc 12

DQc 13

NC 14

VDD 15

VSS 17

DQd 18

DQd 19 VDDQ 20 VSS 21 DQd 22 DQd 23 DQd 24

DQd 25 VSS 26 VDDQ 27 DQd 28 DQd 29 DQPd 30

CY7C1460AV33 1M x 36
80 DQPb NC 1
79 DQb NC 2
78 DQb NC 3
77 VDDQ 4
76 VSS

VSS 5
75 DQb NC 6
74 DQb NC 7
73 DQb 8
72 DQb 9
71 70

VDDQ
10 11
69 DQb 12
68 DQb 13
67 VSS NC
66 NC
65 VDD NC
Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
167 CY7C1460AV33-167AXC

CY7C1462AV33-167AXC

CY7C1460AV33-167BZC

CY7C1460AV33-167AXI

CY7C1464AV33-167BGI
200 CY7C1460AV33-200AXC
250 CY7C1460AV33-250AXC

CY7C1460AV33-250BZC

CY7C1460AV33-250AXI

Package Diagram

Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free

Operating Range

Commercial

Industrial

Commercial

Industrial

Package Diagrams

Figure 100-Pin TQFP 14 x 20 x mm
51-85050 *C

Page 24 of 28 [+] Feedback

Package Diagrams continued

Figure 165-Ball FBGA 15 x 17 x mm

CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
51-85165 *B

Page 25 of 28 [+] Feedback

Package Diagrams continued

Figure 209-Ball FBGA 14 x 22 x mm

CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
51-85167 *A

Page 26 of 28 [+] Feedback

CY7C1460AV33 CY7C1462AV33 CY7C1464AV33

Document History Page

Document Title CY7C1460AV33/CY7C1462AV33/CY7C1464AV33, 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Document Number 38-05353

Orig. of Change

Submission Date

Description of Change
254911

See ECN New Data sheet
Updated the Ordering Information by Shading and Unshading

MPNs as per availability
417509

See ECN Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on

Page# 1 from “3901 North First Street” to “198 Champion Court”

Changed IX current value in MODE from and 30 uA to and 5 uA respectively and also Changed IX current value in ZZ from and 5 uA to and 30 uA respectively on page# 18

Modified test condition from VIH < VDD to VIH < VDD Modified “Input Load” to “Input Leakage Current except ZZ and

MODE” in the

Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the
Ordering

Information table

Replaced Package Diagram of 51-85050 from *A to *B
473229

See ECN Added the Maximum Rating for Supply Voltage on VDDQ Relative
to GND

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table
Updated the Ordering Information table.

Page 27 of 28
[+] Feedback

CY7C1460AV33 CY7C1462AV33 CY7C1464AV33

Document Title CY7C1460AV33/CY7C1462AV33/CY7C1464AV33, 36 Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture Document Number 38-05353
2756998
08/28/09 Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are
available and modified the disclaimer for the Ordering infor-
mation.

Updated Package Diagram for spec
2900822
03/29/2010 Added CY7C1460AV33-167AXI part in Ordering Information

Updated links in Sales, Solutions, and Legal Information

Updated 100-pin TQFP and 209-Ball FBGA package diagrams.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 28 of 28
is the registered trademark and NoBLTM and No Bus LatencyTM are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1464AV33-167BGI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1464AV33-167BGI 508040