CY7C1460AV25-250AXCT

CY7C1460AV25-250AXCT Datasheet

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

Part	Datasheet
CY7C1460AV25-250AXCT	CY7C1460AV25-250AXCT (pdf)

Related Parts	Information
CY7C1460AV25-250BZC	CY7C1460AV25-250BZC
CY7C1464AV25-167BGC	CY7C1464AV25-167BGC
CY7C1460AV25-200BZC	CY7C1460AV25-200BZC

PDF Datasheet Preview
CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture • Pin-compatible and functionally equivalent to ZBT • Supports 250-MHz bus operations with zero wait states Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered inputs and outputs for pipelined operation • Byte Write capability • 2.5V core power supply • 2.5V/1.8V I/O power supply • Fast clock-to-output times ns for 250-MHz device • Clock Enable CEN pin to suspend operation • Synchronous self-timed writes • CY7C1460AV25, CY7C1462AV25 available in JEDEC-standard lead-free 100-pin TQFP package, lead-free and non-lead-free 165-ball FBGA package. CY7C1464AV25 available in lead-free and non-lead-free 209-ball FBGA package • IEEE JTAG-Compatible Boundary Scan • Burst or interleaved burst order • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are 2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst SRAMs with No Bus Latency NoBL logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 equipped with the advanced NoBL logic required to enable consecutive Read/Write operations with data being trans- ferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects for CY7C1464AV25, for CY7C1460AV25 and for CY7C1462AV25 and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block 1M x 36 A0, A1, A MODE ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 ADV/LD BWa BWb BWc BWd WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 167 CY7C1460AV25-167AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1462AV25-167AXC CY7C1460AV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1462AV25-167BZC CY7C1460AV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1462AV25-167BZXC CY7C1464AV25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1464AV25-167BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free CY7C1460AV25-167AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free lndustrial CY7C1462AV25-167AXI CY7C1460AV25-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1462AV25-167BZI CY7C1460AV25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1462AV25-167BZXI CY7C1464AV25-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1464AV25-167BGXI 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free 200 CY7C1460AV25-200AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1462AV25-200AXC CY7C1460AV25-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1462AV25-200BZC CY7C1460AV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1462AV25-200BZXC CY7C1464AV25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1464AV25-200BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free CY7C1460AV25-200AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free lndustrial CY7C1462AV25-200AXI CY7C1460AV25-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1462AV25-200BZI CY7C1460AV25-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1462AV25-200BZXI Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 250 CY7C1460AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1462AV25-250AXC CY7C1460AV25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1462AV25-250BZC CY7C1460AV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1462AV25-250BZXC CY7C1464AV25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1464AV25-250BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free CY7C1460AV25-250AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial CY7C1462AV25-250AXI CY7C1460AV25-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1462AV25-250BZI CY7C1460AV25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1462AV25-250BZXI CY7C1464AV25-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1464AV25-250BGXI 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free Page 23 of 27 [+] Feedback Package Diagrams 100-pin TQFP 14 x 20 x mm 51-85050 100 1 81 80 CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 R MIN. MAX. GAUGE PLANE 0° -7° REF. 30 31 0° MIN. R MIN. MAX. MIN. DETAIL A TYP. 51 50 Updated the Ordering Information by Shading and Unshading MPNs as per availability 417547 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Modified test condition from VDDQ < VDD to VDDQ VDD Changed IX current value in MODE from & 30 µA to & 5 µA respectively and also Changed IX current value in ZZ from & 5 µA to & 30 µA respectively on page# 19 Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from A to B 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Page 27 of 27 [+] Feedback

PDF Datasheet Preview

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25
36-Mbit 1M x 36/2M x 18/512K x 72 Pipelined SRAM with NoBL Architecture
• Pin-compatible and functionally equivalent to ZBT
• Supports 250-MHz bus operations with zero wait states

Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered inputs and outputs for pipelined
operation
• Byte Write capability
• 2.5V core power supply
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
ns for 250-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV25, CY7C1462AV25 available in JEDEC-standard lead-free 100-pin TQFP package, lead-free and non-lead-free 165-ball FBGA package. CY7C1464AV25 available in lead-free and non-lead-free 209-ball FBGA package
• IEEE JTAG-Compatible Boundary Scan
• Burst or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipelined burst

SRAMs with No Bus Latency NoBL logic, respectively.

They are designed to support unlimited true back-to-back

Read/Write operations with no wait states. The

CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
equipped with the advanced NoBL logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent

Write/Read
transitions.

CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects for CY7C1464AV25, for CY7C1460AV25 and for CY7C1462AV25 and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

Logic Block 1M x 36

A0, A1, A

MODE

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

ADV/LD

BWa BWb BWc BWd

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
167 CY7C1460AV25-167AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1462AV25-167AXC

CY7C1460AV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1462AV25-167BZC

CY7C1460AV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1462AV25-167BZXC

CY7C1464AV25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1464AV25-167BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

CY7C1460AV25-167AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
lndustrial

CY7C1462AV25-167AXI

CY7C1460AV25-167BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1462AV25-167BZI

CY7C1460AV25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1462AV25-167BZXI

CY7C1464AV25-167BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1464AV25-167BGXI
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free
200 CY7C1460AV25-200AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1462AV25-200AXC

CY7C1460AV25-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1462AV25-200BZC

CY7C1460AV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1462AV25-200BZXC

CY7C1464AV25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1464AV25-200BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

CY7C1460AV25-200AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
lndustrial

CY7C1462AV25-200AXI

CY7C1460AV25-200BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1462AV25-200BZI

CY7C1460AV25-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1462AV25-200BZXI
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
250 CY7C1460AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1462AV25-250AXC

CY7C1460AV25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1462AV25-250BZC

CY7C1460AV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1462AV25-250BZXC

CY7C1464AV25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1464AV25-250BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

CY7C1460AV25-250AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Industrial

CY7C1462AV25-250AXI

CY7C1460AV25-250BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1462AV25-250BZI

CY7C1460AV25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1462AV25-250BZXI

CY7C1464AV25-250BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1464AV25-250BGXI
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Lead-Free

Page 23 of 27 [+] Feedback

Package Diagrams
100-pin TQFP 14 x 20 x mm 51-85050
100 1
81 80

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

R MIN. MAX.

GAUGE PLANE
0° -7°

REF.
30 31
0° MIN.

R MIN. MAX.

MIN.

DETAIL A

TYP.
51 50
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
417547 See ECN

RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Modified test condition from VDDQ < VDD to VDDQ VDD Changed IX current value in MODE from & 30 µA to & 5 µA respectively and also Changed IX current value in ZZ from & 5 µA to & 30 µA respectively on page# 19

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering

Information table

Replaced Package Diagram of 51-85050 from *A to *B
473650 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

AC Switching Characteristics table.
Updated the Ordering Information table.

Page 27 of 27 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1460AV25-250AXCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1460AV25-250AXCT 508039