CY7C1441AV33-133AXCT

CY7C1441AV33-133AXCT Datasheet

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33

Part	Datasheet
CY7C1441AV33-133AXCT	CY7C1441AV33-133AXCT (pdf)

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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM • Supports 133-MHz bus operations • 1M x 36/2M x 18/512K x 72 common IO • 3.3V core power supply • 2.5V or 3.3V IO power supply • Fast clock-to-output times ns 133-MHz version • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • CY7C1441AV33, CY7C1443AV33 available in JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and non-lead-free 165-ball FBGA package. CY7C1447AV33 available in Pb-free and non-lead-free 209-ball FBGA package • IEEE JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode option Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Functional Description The are 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BWx, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. 133 MHz 310 120 100 MHz Unit Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Logic Block Diagram CY7C1441AV33 1M x 36 A 0, A1, A MODE ADV CLK ADSC ADSP BW D BW A BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A [1:0] BURST Q1 COUNTER AND LOGIC DQ D, DQP D BYTE WRITE REGISTER DQ C, DQP C BYTE WRITE REGISTER DQ B, DQP B BYTE WRITE REGISTER DQ A, DQPA BYTE WRITE REGISTER ENABLE REGISTER DQ D, DQP D BYTE WRITE REGISTER Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 133 CY7C1441AV33-133AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-free Commercial CY7C1443AV33-133AXC CY7C1441AV33-133BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1443AV33-133BZC CY7C1441AV33-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-free CY7C1443AV33-133BZXC CY7C1447AV33-133BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1447AV33-133BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-free CY7C1441AV33-133AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-free lndustrial CY7C1443AV33-133AXI CY7C1441AV33-133BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1443AV33-133BZI CY7C1441AV33-133BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-free CY7C1443AV33-133BZXI CY7C1447AV33-133BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1447AV33-133BGXI 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-free 100 CY7C1441AV33-100AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-free Commercial CY7C1443AV33-100AXC CY7C1441AV33-100BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1443AV33-100BZC CY7C1441AV33-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-free CY7C1443AV33-100BZXC CY7C1447AV33-100BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm CY7C1447AV33-100BGXC 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-free CY7C1441AV33-100AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-free lndustrial CY7C1443AV33-100AXI CY7C1441AV33-100BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm CY7C1443AV33-100BZI CY7C1441AV33-100BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-free CY7C1443AV33-100BZXI Ordering Information 320813 See ECN SYT Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical Characteristics table. Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values. Replaced TBD’s for ΘJA and ΘJC to their respective values for 165 fBGA and 209 fBGA packages on the Thermal Resistance table. Changed CIN,CCLK and CIO to 3 and pF from 5, 5 and 7 pF for TQFP Package. Removed “Lead-free BG and BZ packages availability” comment below the Ordering Information 331551 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA Packages as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBD to 100 mA for IDDZZ Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package. Added Industrial Temperature Grade Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by shading and unshading MPNs as per avail- ability Page 30 of 31 [+] Feedback CY7C1441AV33 CY7C1443AV33,CY7C1447AV33 Document Title CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Document Number 38-05357 Orig. of ECN NO. Issue Date Change Description of Change 417547 See ECN RXU Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court”. Changed IX current value in MODE from & 30 uA to & 5 uA respectively and also Changed IX current value in ZZ from & 5 uA to & 30 uA respectively on page# Modified test condition in note# 8 from VIH < VDD to VIH < VDD. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Information table. Replaced Package Diagram of 51-85050 from A to B Updated the Ordering Information. 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. 2447027 See ECN VKN/AESA Corrected typo in the Ordering Information table Corrected typo in the CY7C1447AV33 ‘s Logic Block diagram Updated the x72 block diagram Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 31 of 31 i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

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CY7C1441AV33 CY7C1443AV33,CY7C1447AV33
36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM
• Supports 133-MHz bus operations
• 1M x 36/2M x 18/512K x 72 common IO
• 3.3V core power supply
• 2.5V or 3.3V IO power supply
• Fast clock-to-output times
ns 133-MHz version
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• CY7C1441AV33, CY7C1443AV33 available in

JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and non-lead-free 165-ball FBGA package. CY7C1447AV33 available in Pb-free and non-lead-free 209-ball FBGA package
• IEEE JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option

Selection Guide

Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current

Functional Description

The are 3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BWx, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
133 MHz 310 120
100 MHz

Unit

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33

Logic Block Diagram CY7C1441AV33 1M x 36

A 0, A1, A MODE ADV CLK

ADSC ADSP BW D

BW A BWE

GW CE1 CE2 CE3 OE

ADDRESS REGISTER

A [1:0]

BURST Q1

COUNTER

AND LOGIC

DQ D, DQP D BYTE

WRITE REGISTER

DQ C, DQP C BYTE

WRITE REGISTER

DQ B, DQP B BYTE

WRITE REGISTER

DQ A, DQPA BYTE

WRITE REGISTER

ENABLE REGISTER

DQ D, DQP D BYTE

WRITE REGISTER
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
133 CY7C1441AV33-133AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-free

Commercial

CY7C1443AV33-133AXC

CY7C1441AV33-133BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1443AV33-133BZC

CY7C1441AV33-133BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-free

CY7C1443AV33-133BZXC

CY7C1447AV33-133BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1447AV33-133BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-free

CY7C1441AV33-133AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-free
lndustrial

CY7C1443AV33-133AXI

CY7C1441AV33-133BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1443AV33-133BZI

CY7C1441AV33-133BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-free

CY7C1443AV33-133BZXI

CY7C1447AV33-133BGI 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1447AV33-133BGXI
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-free
100 CY7C1441AV33-100AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-free

Commercial

CY7C1443AV33-100AXC

CY7C1441AV33-100BZC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1443AV33-100BZC

CY7C1441AV33-100BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-free

CY7C1443AV33-100BZXC

CY7C1447AV33-100BGC 51-85167 209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm

CY7C1447AV33-100BGXC
209-ball Fine-Pitch Ball Grid Array 14 x 22 x mm Pb-free

CY7C1441AV33-100AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-free
lndustrial

CY7C1443AV33-100AXI

CY7C1441AV33-100BZI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm

CY7C1443AV33-100BZI

CY7C1441AV33-100BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array 15 x 17 x mm Pb-free

CY7C1443AV33-100BZXI
Ordering Information
320813 See ECN

SYT Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209 FBGA

Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical

Characteristics table.

Replaced the TBD’s for IDD, ISB1, ISB2, ISB3 and ISB4 to their respective values. Replaced TBD’s for ΘJA and ΘJC to their respective values for 165 fBGA and 209 fBGA packages on the Thermal Resistance table.

Changed CIN,CCLK and CIO to 3 and pF from 5, 5 and 7 pF for TQFP Package.

Removed “Lead-free BG and BZ packages availability” comment below the
Ordering Information
331551 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209 BGA

Packages as per JEDEC standards and updated the Pin Definitions accordingly

Modified VOL, VOH test conditions Replaced TBD to 100 mA for IDDZZ Changed CIN, CCLK and CIO to 7, 7and 6 pF from 5, 5 and 7 pF for 165 FBGA Package.

Added Industrial Temperature Grade
Changed ISB2 and ISB4 from 100 and 110 mA to 120 and 135 mA respectively Updated the Ordering Information by shading and unshading MPNs as per avail-
ability

Page 30 of 31 [+] Feedback

CY7C1441AV33 CY7C1443AV33,CY7C1447AV33

Document Title CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 36-Mbit 1M x 36/2M x 18/512K x 72 Flow-Through SRAM Document Number 38-05357

Orig. of ECN NO. Issue Date Change

Description of Change
417547 See ECN RXU Converted from Preliminary to Final.

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

North First Street” to “198 Champion Court”.

Changed IX current value in MODE from & 30 uA to & 5 uA respectively and also Changed IX current value in ZZ from & 5 uA to & 30 uA respectively on page#

Modified test condition in note# 8 from VIH < VDD to VIH < VDD. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table.
Replaced Package Name column with Package Diagram in the Ordering

Information table.

Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information.
473650 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

Switching Characteristics table.
Updated the Ordering Information table.
2447027 See ECN VKN/AESA Corrected typo in the Ordering Information table

Corrected typo in the CY7C1447AV33 ‘s Logic Block diagram

Updated the x72 block diagram

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 31 of 31
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1441AV33-133AXCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1441AV33-133AXCT 508037