CY7C1444AV33-167AXCT

CY7C1444AV33-167AXCT Datasheet

CY7C1444AV33 CY7C1445AV33

Part	Datasheet
CY7C1444AV33-167AXCT	CY7C1444AV33-167AXCT (pdf)

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CY7C1444AV33 CY7C1445AV33 36-Mbit 1 M x 36/2 M x 18 Pipelined DCD Sync SRAM 36-Mbit 1 M x 36/2 M x 18 Pipelined DCD Sync SRAM • Supports bus operation up to 250 MHz • Available speed grades are 250, 200, and 167 MHz • Registered inputs and outputs for pipelined operation • Optimal for performance double-cycle deselect • Depth expansion without wait state • V core power supply • V/3.3 V I/O power supply • Fast clock-to-output times ns for 250-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • CY7C1444AV33, CY7C1445AV33 available in JEDEC-standard Pb-free 100-pin TQFP package and Pb-free and non Pb-free 165-ball FBGA package • IEEE JTAG-compatible boundary scan • “ZZ” sleep mode option Functional Description[1] The CY7C1444AV33/CY7C1445AV33 SRAM integrates 1 M x 36/2 M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3 , burst control inputs ADSC, ADSP, and ADV , write enables BWX, and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. This part supports byte write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1444AV33/CY7C1445AV33 operates from a V core power supply while all outputs operate with a V or a V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1444AV33 CY7C1445AV33 Logic Block Diagram CY7C1444AV33 1 M x 36 A0,A1,A MODE ADV CLK ADSC ADSP BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER 2 A[1:0] BURST Q1 COUNTER AND LOGIC CLR Q0 DQD,DQPD BYTE WRITE REGISTER DQc,DQPC BYTE WRITE REGISTER DQB,DQPB BYTE WRITE REGISTER DQA,DQPA BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE DQD,DQPD BYTE WRITE DRIVER DQc,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE DRIVER Read Cycle Timing 20 Write Cycle Timing 21 Read/Write Cycle Timing 22 ZZ Mode Timing 23 Ordering Information 24 Ordering Code Definitions 24 Package Diagram 25 Acronyms 26 Document Conventions 26 Units of Measure 26 Document History Page 27 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28 Page 3 of 28 [+] Feedback CY7C1444AV33 CY7C1445AV33 Selection Guide Maximum access time Maximum operating current Maximum CMOS standby current Pin Configurations 250 MHz 200 MHz 167 MHz Unit 100-pin TQFP Pinout ADSP ADSC ADSP ADSC DQPC VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ DQPD CY7C1444AV33 1 M x 36 DQPB 77 76 75 VDDQ VSSQ DQB VDDQ VSSQ 73 72 71 70 69 68 67 DQB VSSQ VDDQ DQB VSS DQB VSSQ VDDQ DQB VDD NC 64 63 62 61 60 59 58 57 56 ZZ DQA VDDQ VSSQ DQA VSS DQB VDDQ VSSQ DQB DQPB 55 54 53 VSSQ VDDQ DQA VSSQ VDDQ DQPA Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at t Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 167 CY7C1444AV33-167AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free Commercial Ordering Code Definitions CY7C 1444 A V33 - 167 AX C Temperature range C = Commercial Package Type AX = 100-pin TQFP Pb-free Speed Grade 167 MHz V33 = V Process Technology 90 nm 1444 = DCD, 1 Mb x 36 Mb CY7C = Cypress SRAMs Page 24 of 28 [+] Feedback Package Diagram CY7C1444AV33 CY7C1445AV33 51-85050 C Page 25 of 28 [+] Feedback Acronyms Acronym CE CEN FPBGA I/O JTAG NoBL OE SRAM TCK TMS TDI TDO TQFP WE Description chip enable clock enable fine-pitch ball grid array input/output Joint Test Action Group No Bus Latency output enable static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable CY7C1444AV33 CY7C1445AV33 Document Conventions Units of Measure Symbol ns V µA mA ms MHz pF W °C Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds Mega Hertz pico Farad Watts degree Celcius Page 26 of 28 [+] Feedback CY7C1444AV33 CY7C1445AV33 Document History Page Document Title CY7C1444AV33/CY7C1445AV33 36-Mbit 1 M x 36/2 M x 18 Pipelined DCD Sync SRAM Document Number 38-05352 ECN NO. Submission Date Orig. of Change Description of Change 124419 03/04/03 CGM New data sheet 254910 See ECN differ by the letter “A” Modified Functional Block diagrams Modified switching waveforms Added boundary scan information Added footnote #13 32-Bit Vendor I.D Code changed Added IDD, IX and ISB values in DC Electrical Characteristics Added tPOWER specifications in Switching Characteristics table Removed 119 PBGA package Changed 165 FBGA package from BB165 15 x 17 x mm to BB165C 15 x 17 x mm 303533 See ECN SYT Changed the test condition from VDD = Min. to VDD = Max for VOL in the Electrical Characteristics table Replaced and from TBD to respective Thermal Values for All Packages on the Thermal Resistance Table Updated the Ordering Information by Shading and Unshading MPNs as per availability 417509 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed IX current value in MODE from & 30 to & 5 respectively and also Changed IX current value in ZZ from & 5 to & 30 respectively on page# 16 Modified test condition from VIH < VDD to VIH VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from A to *B Page 27 of 28 [+] Feedback CY7C1444AV33 CY7C1445AV33 Document Title CY7C1444AV33/CY7C1445AV33 36-Mbit 1 M x 36/2 M x 18 Pipelined DCD Sync SRAM Document Number 38-05352 ECN NO. Submission Date Orig. of Change Description of Change 473229 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table. 2898663 03/24/2010 NJY Removed inactive parts from Ordering Information table. Updated package diagram. 3042209 09/29/2010 NJY Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 28 of 28 [+] Feedback

PDF Datasheet Preview

CY7C1444AV33 CY7C1445AV33
36-Mbit 1 M x 36/2 M x 18 Pipelined DCD Sync SRAM
36-Mbit 1 M x 36/2 M x 18 Pipelined DCD Sync SRAM
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance double-cycle deselect
• Depth expansion without wait state
• V core power supply
• V/3.3 V I/O power supply
• Fast clock-to-output times
ns for 250-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• CY7C1444AV33, CY7C1445AV33 available in

JEDEC-standard Pb-free 100-pin TQFP package and Pb-free and non Pb-free 165-ball FBGA package
• IEEE JTAG-compatible boundary scan
• “ZZ” sleep mode option

Functional Description[1]

The CY7C1444AV33/CY7C1445AV33 SRAM integrates 1 M x 36/2 M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3 , burst control inputs ADSC, ADSP, and ADV , write enables BWX, and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. This part supports byte write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. The CY7C1444AV33/CY7C1445AV33 operates from a V core power supply while all outputs operate with a V or a V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1444AV33 CY7C1445AV33

Logic Block Diagram CY7C1444AV33 1 M x 36

A0,A1,A MODE

ADV CLK

ADSC ADSP

BWA BWE GW

CE1 CE2 CE3 OE

ADDRESS REGISTER
2 A[1:0]

BURST Q1

COUNTER AND

LOGIC

CLR Q0

DQD,DQPD BYTE

WRITE REGISTER

DQc,DQPC BYTE

WRITE REGISTER

DQB,DQPB BYTE

WRITE REGISTER

DQA,DQPA BYTE

WRITE REGISTER

ENABLE REGISTER

PIPELINED ENABLE

DQD,DQPD BYTE

WRITE DRIVER

DQc,DQPC BYTE

WRITE DRIVER

DQB,DQPB BYTE

WRITE DRIVER
Read Cycle Timing 20 Write Cycle Timing 21 Read/Write Cycle Timing 22 ZZ Mode Timing 23 Ordering Information 24 Ordering Code Definitions 24 Package Diagram 25 Acronyms 26 Document Conventions 26 Units of Measure 26 Document History Page 27 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28

Page 3 of 28 [+] Feedback

CY7C1444AV33 CY7C1445AV33

Selection Guide

Maximum access time Maximum operating current Maximum CMOS standby current

Pin Configurations
250 MHz
200 MHz
167 MHz

Unit
100-pin TQFP Pinout

ADSP

ADSC

ADSP

ADSC

DQPC

VDDQ

VSSQ

VSSQ

VDDQ

VDDQ

VSSQ

VSSQ

VDDQ

DQPD

CY7C1444AV33 1 M x 36

DQPB
77 76 75

VDDQ VSSQ DQB

VDDQ VSSQ
73 72 71 70 69 68 67

DQB VSSQ VDDQ DQB VSS

DQB VSSQ VDDQ DQB

VDD NC
64 63 62 61 60 59 58 57 56

ZZ DQA VDDQ VSSQ DQA

VSS DQB VDDQ VSSQ DQB DQPB
55 54 53

VSSQ VDDQ DQA

VSSQ VDDQ

DQPA
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at t

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
167 CY7C1444AV33-167AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free

Commercial
Ordering Code Definitions CY7C 1444 A V33 - 167 AX C

Temperature range C = Commercial Package Type AX = 100-pin TQFP Pb-free Speed Grade 167 MHz V33 = V Process Technology 90 nm 1444 = DCD, 1 Mb x 36 Mb CY7C = Cypress SRAMs

Page 24 of 28 [+] Feedback

Package Diagram

CY7C1444AV33 CY7C1445AV33
51-85050 *C

Page 25 of 28 [+] Feedback

Acronyms

Acronym CE CEN FPBGA I/O JTAG NoBL OE SRAM TCK TMS TDI TDO TQFP WE

Description chip enable clock enable fine-pitch ball grid array input/output Joint Test Action Group No Bus Latency output enable static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable

CY7C1444AV33 CY7C1445AV33

Document Conventions

Units of Measure

Symbol ns V µA mA ms MHz pF W °C

Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds Mega Hertz pico Farad Watts degree Celcius

Page 26 of 28 [+] Feedback

CY7C1444AV33 CY7C1445AV33

Document History Page

Document Title CY7C1444AV33/CY7C1445AV33 36-Mbit 1 M x 36/2 M x 18 Pipelined DCD Sync SRAM Document Number 38-05352

ECN NO.

Submission Date

Orig. of Change

Description of Change
124419
03/04/03

CGM New data sheet
254910 See ECN
differ by the letter “A”

Modified Functional Block diagrams

Modified switching waveforms

Added boundary scan information

Added footnote #13 32-Bit Vendor I.D Code changed

Added IDD, IX and ISB values in DC Electrical Characteristics Added tPOWER specifications in Switching Characteristics table Removed 119 PBGA package

Changed 165 FBGA package from BB165 15 x 17 x mm to

BB165C
15 x 17 x mm
303533 See ECN

SYT Changed the test condition from VDD = Min. to VDD = Max for VOL in the

Electrical Characteristics table

Replaced and from TBD to respective Thermal Values for All

Packages on the Thermal Resistance Table
Updated the Ordering Information by Shading and Unshading MPNs as
per availability
417509 See ECN

RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”

Changed IX current value in MODE from & 30 to & 5 respectively and also Changed IX current value in ZZ from & 5 to & 30 respectively on page# 16

Modified test condition from VIH < VDD to VIH VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE”
in the

Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the
Ordering

Information table

Replaced Package Diagram of 51-85050 from *A to *B

Page 27 of 28
[+] Feedback

CY7C1444AV33 CY7C1445AV33

Document Title CY7C1444AV33/CY7C1445AV33 36-Mbit 1 M x 36/2 M x 18 Pipelined DCD Sync SRAM Document Number 38-05352

ECN NO.

Submission Date

Orig. of Change

Description of Change
473229 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table
Updated the Ordering Information table.
2898663 03/24/2010
NJY Removed inactive parts from Ordering Information table. Updated
package diagram.
3042209 09/29/2010
NJY Added Ordering Code Definitions.

Added Acronyms and Units of Measure.

Minor edits and updated in new template.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

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Datasheet ID: CY7C1444AV33-167AXCT 508034