CY7C145-35JXC

CY7C145-35JXC Datasheet


CY7C144, CY7C145

Part Datasheet
CY7C145-35JXC CY7C145-35JXC CY7C145-35JXC (pdf)
Related Parts Information
CY7C144-15JXCT CY7C144-15JXCT CY7C144-15JXCT
CY7C144-15JXC CY7C144-15JXC CY7C144-15JXC
CY7C144-55JC CY7C144-55JC CY7C144-55JC
PDF Datasheet Preview
CY7C144, CY7C145
8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY
• True Dual-Ported Memory Cells that Enable Simultaneous Reads of the same Memory Location
• 8K x 8 Organization CY7C144
• 8K x 9 Organization CY7C145
• 0.65-Micron CMOS for optimum Speed and Power
• High Speed Access 15 ns
• Low Operating Power ICC = 160 mA max.
• Fully Asynchronous Operation
• Automatic Power Down
• TTL Compatible
• Master/Slave Select Pin enables Bus Width Expansion to 16/18

Bits or more
• Busy Arbitration Scheme provided
• Semaphores included to permit Software Handshaking
between Ports
• INT Flag for Port-to-Port Communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP
• Pb-free Packages available

Functional Description

The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and 8K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C144/5 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C144/5 can be used as a standalone 64/72-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags, BUSY and INT, are provided on each port. BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a chip enable CE pin or SEM pin.

Logic Block Diagram R/W L

R/W R

CE L OE L

CE R OER
7C145 I/O8L I/O7L I/O0L

BUSYL[1, 2] A 12L

I/O CONTROL

I/O CONTROL

ADDRESS DECODER

MEMORY ARRAY

ADDRESS DECODER

I/O 8R 7C145 I/O 7R I/O 0R BUSYR [1, 2]

A 12R

SEM L INT L[2]

CEL OEL R/W L

Notes BUSY is an output in master mode and an input in slave mode. Interrupt push-pull output and requires no pull-up resistor.

INTERRUPT SEMAPHORE ARBITRATION

CE R OE R/W R

SEMR INTR [2]
• San Jose, CA 95134-1709
• 408-943-2600
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Pin Configuration

Figure 68-Pin PLCC Top View

CY7C144, CY7C145

Figure 64-Pin TQFP Top View

A10L

A11L

A12L

SEML

R/WL

IO 0L

IO 1L
Ordering Information
8K x8 Dual-Port SRAM

Speed ns
Ordering Code

CY7C144-15AC

CY7C144-15AXC

CY7C144-15JC

CY7C144-15JXC

CY7C144-15AI

CY7C144-15JXI

CY7C144-15AXI

CY7C144-25AC

CY7C144-25AXC

CY7C144-25JC

CY7C144-25AI

CY7C144-25JI

CY7C144-35AC

CY7C144-35JC

CY7C144-35AI

CY7C144-35JI

CY7C144-55AC

CY7C144-55AXC

CY7C144-55JC

CY7C144-55JXC

CY7C144-55AI

CY7C144-55JI
8K x9 Dual-Port SRAM

CY7C145-15AC

CY7C145-15AXC

CY7C145-15JC

CY7C145-25AC

CY7C145-25JC

CY7C145-25AI

CY7C145-25JI

CY7C145-35AC

CY7C145-35JC

CY7C145-35JXC

CY7C145-35AI

CY7C145-35JI

CY7C145-55AC

CY7C145-55JC

CY7C145-55AI

CY7C145-55JI

CY7C144, CY7C145
ordering information section
393320

See ECN Added Pb-Free Logo
Added Pb-Free parts to ordering information:

CY7C144-15AXC, CY7C144-15JXC, CY7C144-15AXI, CY7C144-25AXC,

CY7C144-55AXC, CY7C144-55JXC, CY7C145-15AXC, CY7C145-35JXC
2623658 VKN/PYRS 12/17/2008 Added CY7C144-15JXI in the Ordering information table
2699693 VKN/PYRS 04/29/2009 Corrected defective Logic Block diagram, Pinouts and Package diagrams

Sales, Solutions and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
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PSoC Solutions

General
psoc.cypress.com/solutions

Low Power/Low Voltage
psoc.cypress.com/low-power

Precision Analog
psoc.cypress.com/precision-analog

LCD Drive
psoc.cypress.com/lcd-drive

CAN 2.0b
psoc.cypress.com/can
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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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Datasheet ID: CY7C145-35JXC 508033