CY7C1423BV18-250BZC
CY7C1423BV18-250BZC Datasheet
CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18
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CY7C1423BV18-250BZC |
CY7C1423BV18-250BZC (pdf) |
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| CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Functional Description • 36-Mbit density 4M x 8, 4M x 9, 2M x 18, 1M x 36 • 300 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double Data Rate DDR interfaces data transferred at 600 MHz at 300 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock skew and flight time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Synchronous internally self-timed writes • DDR-II operates with cycle read latency when the DLL is enabled • Operates similar to a DDR-I device with 1 cycle read latency in DLL off mode • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage • Available in 165-Ball FBGA package 15 x 17 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO DDR-II SIO architecture. The DDR-II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1422BV18, two 9-bit words in the case of CY7C1429BV18, two 18-bit words in the case of CY7C1423BV18, and two 36-bit words in the case of CY7C1424BV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. CY7C1422BV18 4M x 8 CY7C1429BV18 4M x 9 CY7C1423BV18 2M x 18 CY7C1424BV18 1M x 36 Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 278 MHz 278 775 815 890 250 MHz 250 700 740 800 200 MHz 200 600 665 167 MHz 167 500 560 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Logic Block Diagram CY7C1422BV18 8 D[7:0] A 20:0 21 Address Register K DOFF CLK Gen. R/W VREF NWS[1:0] Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 300 CY7C1422BV18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429BV18-300BZC CY7C1423BV18-300BZC CY7C1424BV18-300BZC CY7C1422BV18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429BV18-300BZXC CY7C1423BV18-300BZXC CY7C1424BV18-300BZXC CY7C1422BV18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429BV18-300BZI CY7C1423BV18-300BZI CY7C1424BV18-300BZI CY7C1422BV18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429BV18-300BZXI CY7C1423BV18-300BZXI CY7C1424BV18-300BZXI 278 CY7C1422BV18-278BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429BV18-278BZC CY7C1423BV18-278BZC CY7C1424BV18-278BZC CY7C1422BV18-278BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429BV18-278BZXC CY7C1423BV18-278BZXC CY7C1424BV18-278BZXC CY7C1422BV18-278BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429BV18-278BZI Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1422BV18-250BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429BV18-250BZC CY7C1423BV18-250BZC CY7C1424BV18-250BZC CY7C1422BV18-250BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429BV18-250BZXC CY7C1423BV18-250BZXC CY7C1424BV18-250BZXC CY7C1422BV18-250BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429BV18-250BZI CY7C1423BV18-250BZI CY7C1424BV18-250BZI CY7C1422BV18-250BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429BV18-250BZXI CY7C1423BV18-250BZXI CY7C1424BV18-250BZXI 200 CY7C1422BV18-200BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429BV18-200BZC CY7C1423BV18-200BZC CY7C1424BV18-200BZC CY7C1422BV18-200BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429BV18-200BZXC CY7C1423BV18-200BZXC CY7C1424BV18-200BZXC CY7C1422BV18-200BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429BV18-200BZI Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1422BV18-167BZC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1429BV18-167BZC CY7C1423BV18-167BZC CY7C1424BV18-167BZC CY7C1422BV18-167BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429BV18-167BZXC CY7C1423BV18-167BZXC CY7C1424BV18-167BZXC CY7C1422BV18-167BZI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1429BV18-167BZI CY7C1423BV18-167BZI CY7C1424BV18-167BZI CY7C1422BV18-167BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array 15 x 17 x mm Pb-Free CY7C1429BV18-167BZXI CY7C1423BV18-167BZXI CY7C1424BV18-167BZXI Page 28 of 30 [+] Feedback Package Diagram CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Figure 165-ball FBGA 15 x 17 x mm , 51-85195 ! " # % & ' * + , 0 2 ! " # % & ' * + , 0 2 51-85195-*A Page 29 of 30 [+] Feedback CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18 Document History Page Document Title 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Document Number 001-07035 ECN NO. SUBMISSION DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE |
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