CY7C1393CV18-250BZXC

CY7C1393CV18-250BZXC Datasheet

CY7C1393CV18 CY7C1394CV18

Part	Datasheet
CY7C1393CV18-250BZXC	CY7C1393CV18-250BZXC (pdf)

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CY7C1393CV18 CY7C1394CV18 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture Functional Description • 18-Mbit Density 1M x 18, 512K x 36 • 300 MHz Clock for high Bandwidth • 2-word Burst for reducing Address Bus Frequency • Double Data Rate DDR Interfaces data transferred at 600 MHz at 300 MHz • Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only • Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches • Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems • Synchronous internally Self-timed Writes • DDR II operates with Cycle Read Latency when the DLL is enabled • Operates similar to a DDR I Device with one Cycle Read Latency in DLL Off Mode • 1.8V Core Power Supply with HSTL Inputs and Outputs • Variable Drive HSTL Output Buffers • Expanded HSTL Output Voltage • Available in 165-Ball FBGA Package 13 x 15 x mm • Offered in both Pb-free and non Pb-free Packages • JTAG compatible Test Access Port • Delay Lock Loop DLL for accurate Data Placement The CY7C1393CV18, and CY7C1394CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O DDR II SIO architecture. The DDR II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 18-bit words in the case of CY7C1393CV18, and two 36-bit words in the case of CY7C1394CV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations CY7C1393CV18 1M x 18 CY7C1394CV18 512K x 36 Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 278 MHz 278 800 850 250 MHz 250 725 770 200 MHz 200 600 630 167 MHz 167 500 540 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1393CV18 CY7C1394CV18 Logic Block Diagram CY7C1393CV18 D[17:0] A 18:0 19 Address Register K DOFF CLK Gen. Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 250 CY7C1393CV18-250BZXC Package Diagram Package Type Operating Range 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Commercial Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B - 01.0665X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180-B Page 24 of 25 [+] Feedback CY7C1393CV18 CY7C1394CV18 Document History Page Document Title CY7C1393CV18/CY7C1394CV18, 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture Document Number 001-07162 ECN No. Submission Date Orig. of Change Description of Change * 433284 See ECN NXR New data sheet A 462615 See ECN Changed tCYC from 100 ns to 50 ns, changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform B 1523386 C 2507766 See ECN 05/23/08 VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated IDD/ISB specs, Changed DLL minimum operating frequency from 80MHz to 120MHz, Changed tCYC max spec to 8.4ns for all speed bins, Modified footnotes 20 and VKN/PYRS Changed Ambient Temperature with Power Applied from to +85°C” to +125°C” in the “Maximum Ratings“ on page 20, Updated power up sequence waveform and its description, Added footnote #19 related to IDD, Changed ΘJA spec from to Changed ΘJC spec from to Changed JTAG ID [31:29] from 001 to D 2755838 08/25/2009 VKN/AESA Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 25 of 25 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1393CV18 CY7C1394CV18
18-Mbit DDR II SIO SRAM 2-Word Burst Architecture

Functional Description
• 18-Mbit Density 1M x 18, 512K x 36
• 300 MHz Clock for high Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate DDR Interfaces data transferred at 600 MHz at 300 MHz
• Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only
• Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches
• Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems
• Synchronous internally Self-timed Writes
• DDR II operates with Cycle Read Latency when the DLL is enabled
• Operates similar to a DDR I Device with one Cycle Read Latency in DLL Off Mode
• 1.8V Core Power Supply with HSTL Inputs and Outputs
• Variable Drive HSTL Output Buffers
• Expanded HSTL Output Voltage
• Available in 165-Ball FBGA Package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free Packages
• JTAG compatible Test Access Port
• Delay Lock Loop DLL for accurate Data Placement

The CY7C1393CV18, and CY7C1394CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O DDR II SIO architecture. The DDR II SIO consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 18-bit words in the case of CY7C1393CV18, and two 36-bit words in the case of CY7C1394CV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR II SIO SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1393CV18 1M x 18 CY7C1394CV18 512K x 36

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
300 MHz
278 MHz 278 800 850
250 MHz 250 725 770
200 MHz 200 600 630
167 MHz 167 500 540

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
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CY7C1393CV18 CY7C1394CV18

Logic Block Diagram CY7C1393CV18

D[17:0]

A 18:0 19

Address Register

K DOFF

CLK Gen.
Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
250 CY7C1393CV18-250BZXC

Package Diagram

Package Type

Operating Range
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Commercial

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B - 01.0665X
11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180-*B

Page 24 of 25 [+] Feedback

CY7C1393CV18 CY7C1394CV18

Document History Page

Document Title CY7C1393CV18/CY7C1394CV18, 18-Mbit DDR II SIO SRAM 2-Word Burst Architecture Document Number 001-07162

ECN No.

Submission Date

Orig. of Change

Description of Change
** 433284 See ECN

NXR New data sheet
*A 462615 See ECN

Changed tCYC from 100 ns to 50 ns, changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform
*B 1523386 *C 2507766

See ECN 05/23/08

VKN/AESA Converted from preliminary to final, Updated Logic Block diagram, Updated IDD/ISB specs, Changed DLL minimum operating frequency from 80MHz to 120MHz, Changed tCYC max spec to 8.4ns for all speed bins, Modified footnotes 20 and

VKN/PYRS Changed Ambient Temperature with Power Applied from to +85°C” to +125°C” in the “Maximum Ratings“ on page 20, Updated power up sequence waveform and its description, Added footnote #19 related to IDD, Changed ΘJA spec from to Changed ΘJC spec from to Changed JTAG ID [31:29] from 001 to
*D 2755838 08/25/2009 VKN/AESA Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 25 of 25

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1393CV18-250BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1393CV18-250BZXC 508008