CY7C1381F-133BGCT
CY7C1381F-133BGCT Datasheet
CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
| Part | Datasheet |
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CY7C1381F-133BGCT |
CY7C1381F-133BGCT (pdf) |
| Related Parts | Information |
|---|---|
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CY7C1383D-100AXC |
CY7C1383D-100AXC |
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CY7C1381F-133BGC |
CY7C1381F-133BGC |
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CY7C1381D-100BZC |
CY7C1381D-100BZC |
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CY7C1381D-133AXIT |
CY7C1381D-133AXIT |
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CY7C1383D-133AXIT |
CY7C1383D-133AXIT |
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CY7C1383D-100AXCT |
CY7C1383D-100AXCT |
| PDF Datasheet Preview |
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| CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F 18-Mbit 512K x 36/1M x 18 Flow-Through SRAM Functional Description [1] • Supports 133 MHz bus operations • 512K x 36 and 1M x 18 common IO • 3.3V core power supply VDD • 2.5V or 3.3V IO supply VDDQ • Fast clock-to-output time ns 133 MHz version • Provides high performance 2-1-1-1 access rate • User selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • CY7C1381D/CY7C1383D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1381F/CY7C1383F available in Pb-free and non Pb-free 119-ball BGA package • IEEE JTAG-Compatible Boundary Scan • ZZ sleep mode option The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a 3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133 MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3 [2] , burst control inputs ADSC, ADSP, and ADV , write enables BWx, and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin. The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F allows interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe ADSP or the cache controller address strobe ADSC inputs. Address advancement is controlled by the address advancement ADV input. Addresses and chip enables are registered at rising edge of clock when address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the advance pin ADV . The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F operates from a +3.3V core power supply while all outputs operate with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. Selection Guide 133 MHz 100 MHz Unit Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Notes For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on CE3, CE2 are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F Logic Block Diagram CY7C1381D/CY7C1381F [3] 512K x 36 A0, A1, A MODE ADV CLK ADSC ADSP BW D BW A BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A [1:0] BURST Q1 COUNTER AND LOGIC DQ D, DQP D BYTE WRITE REGISTER DQ C , DQP C WRITE REGISTER DQ B, DQP B WRITE REGISTER DQ A, DQP A BYTE WRITE REGISTER ENABLE REGISTER Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 133 CY7C1381D-133AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free Commercial CY7C1383D-133AXC CY7C1381F-133BGC 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1383F-133BGC CY7C1381F-133BGXC 51-85115 119-ball Grid Array 14 x 22 x mm Pb-Free CY7C1383F-133BGXC CY7C1381D-133BZC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm CY7C1383D-133BZC CY7C1381D-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1383D-133BZXC CY7C1381D-133AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free lndustrial CY7C1383D-133AXI CY7C1381F-133BGI 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1383F-133BGI CY7C1381F-133BGXI 51-85115 119-ball Grid Array 14 x 22 x mm Pb-Free CY7C1383F-133BGXI CY7C1381D-133BZI 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm CY7C1383D-133BZI CY7C1381D-133BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1383D-133BZXI 100 CY7C1381D-100AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free Commercial CY7C1383D-100AXC CY7C1381F-100BGC 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1383F-100BGC CY7C1381F-100BGXC 51-85115 119-ball Grid Array 14 x 22 x mm Pb-Free CY7C1383F-100BGXC CY7C1381D-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm CY7C1383D-100BZC CY7C1381D-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1383D-100BZXC CY7C1381D-100AXI Added comment of ‘Pb-free BG packages availability’ below the Ordering Infor- mation 326078 See ECN PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed Device Width 23:18 for 119-BGA from to 101001 Added separate row for 165 -FBGA Device Width 23:18 Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to and °C/W respectively Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to and °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to and °C/W respectively Modified VOL, VOH test conditions Removed comment of ‘Pb-free BG packages availability’ below the Ordering Information Updated Ordering Information Table Changed from Preliminary to Final 351895 See ECN PCI Updated Ordering Information Table 416321 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed the description of IX from Input Load Current to Input Leakage Current on page# 18 Changed the IX current values of MODE on page # 18 from µA and 30 µA to µA and 5 µA Changed the IX current values of ZZ on page # 18 from µA and 5 µA to µA and 30 µA Changed VIH < VDD to VIH < VDDon page # 18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table 475009 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. 776456 See ECN VKN Added Part numbers CY7C1381F and CY7C1383F and its related information Added footnote# 3 regarding Chip Enable Updated Ordering Information table Page 29 of 29 [+] Feedback |
| More datasheets: M3440 SL005 | M3440 SL002 | 55444.5 | 55444.4 | 55444.3 | 55444.2 | 55444.1 | QT220-ISSG | CY7C1383D-100AXC | CY7C1381F-133BGC |
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