CY7C1380C-167BZI

CY7C1380C-167BZI Datasheet

CY7C1380C CY7C1382C

Part	Datasheet
CY7C1380C-167BZI	CY7C1380C-167BZI (pdf)

Related Parts	Information
CY7C1380C-167AC	CY7C1380C-167AC
CY7C1380C-133AC	CY7C1380C-133AC
CY7C1382C-167AC	CY7C1382C-167AC

PDF Datasheet Preview
CY7C1380C CY7C1382C 18-Mb 512K x 36/1M x 18 Pipelined SRAM Functional Description[1] • Supports bus operation up to 250 MHz • Available speed grades are 250, 225, 200,166 and 133MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V / 3.3V I/O operation • Fast clock-to-output times ns for 250-MHz device ns for 225-MHz device ns for 200-MHz device ns for 166-MHz device ns for 133-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages • IEEE JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable Enables CE2 and CE3 [2] , Burst CCoEn1t r,oldienpptuht-se xApDanSsCio, nADCShPip, a GndWA .DAVs y, BWE , and the Output Global Enable Write OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1380C/CY7C1382C operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3 , CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable. Unit ns mA Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C1380C CY7C1382C Logic Block Diagram CY7C1380C 512K x 36 A0, A1, A MODE ADV CLK ADSC ADSP BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER Ordering Information Speed MHz Ordering Code CY7C1380C-250AC CY7C1382C-250AC CY7C1380C-250BGC CY7C1382C-250BGC CY7C1380C-250BZC CY7C1382C-250BZC CY7C1380C-225AC CY7C1382C-225AC CY7C1380C-225BGC CY7C1382C-225BGC CY7C1380C-225BZC CY7C1382C-225BZC CY7C1380C-200AC CY7C1382C-200AC CY7C1380C-200BGC CY7C1382C-200BGC CY7C1380C-200BZC CY7C1382C-200BZC CY7C1380C-167AC CY7C1382C-167AC CY7C1380C-167BGC CY7C1382C-167BGC CY7C1380C-167BZC CY7C1382C-167BZC CY7C1380C-133AC Package Name Part and Package Type A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm BG119 119 PBGA BB165A 165 fBGA A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm BG119 119 PBGA BB165A 165 fBGA A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm BG119 119 PBGA BB165A 165 fBGA A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm BG119 119 PBGA BB165A 165 fBGA A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 167 CY7C1380C-167AI CY7C1382C-167AI A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm CY7C1380C-167BGI CY7C1382C-167BGI BG119 119 PBGA CY7C1380C-167BZI BB165A 165 fBGA CY7C1382C-167BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Operating Range Commercial Industrial Page 32 of 36 Updated Ordering Information 128904 09/11/03 DPM Changed ordering of notes Updated JTAG Boundary Scan order Removed Pipelined Read/Write Timing diagram Added tPOWER specification in Switching Characteristics table 206081 02/13/04 RKF Final Datasheet Page 36 of 36

PDF Datasheet Preview

CY7C1380C CY7C1382C
18-Mb 512K x 36/1M x 18 Pipelined SRAM

Functional Description[1]
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 225, 200,166 and
133MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
ns for 250-MHz device ns for 225-MHz device ns for 200-MHz device ns for 166-MHz device ns for 133-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages
• IEEE JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option

The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input CLK . The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable Enables CE2 and CE3 [2] , Burst

CCoEn1t r,oldienpptuht-se xApDanSsCio, nADCShPip,
a GndWA .DAVs y,

BWE , and the Output

Global Enable

Write OE
and the ZZ pin.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by
the Advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1380C/CY7C1382C operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide
250 MHz 225 MHz 200 MHz 167 MHz 133 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3 , CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

Unit ns mA

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C1380C CY7C1382C

Logic Block Diagram CY7C1380C 512K x 36

A0, A1, A

MODE ADV CLK

ADSC ADSP

BWA BWE GW

CE1 CE2 CE3 OE

ADDRESS REGISTER
Ordering Information

Speed MHz
Ordering Code

CY7C1380C-250AC CY7C1382C-250AC

CY7C1380C-250BGC CY7C1382C-250BGC

CY7C1380C-250BZC CY7C1382C-250BZC

CY7C1380C-225AC

CY7C1382C-225AC

CY7C1380C-225BGC CY7C1382C-225BGC

CY7C1380C-225BZC CY7C1382C-225BZC

CY7C1380C-200AC CY7C1382C-200AC

CY7C1380C-200BGC

CY7C1382C-200BGC

CY7C1380C-200BZC

CY7C1382C-200BZC

CY7C1380C-167AC CY7C1382C-167AC

CY7C1380C-167BGC

CY7C1382C-167BGC

CY7C1380C-167BZC CY7C1382C-167BZC

CY7C1380C-133AC

Package Name

Part and Package Type

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm

BG119 119 PBGA

BB165A 165 fBGA

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm

BG119 119 PBGA BB165A 165 fBGA

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm BG119 119 PBGA

BB165A 165 fBGA

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm BG119 119 PBGA

BB165A 165 fBGA A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm
167 CY7C1380C-167AI CY7C1382C-167AI

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm

CY7C1380C-167BGI CY7C1382C-167BGI

BG119 119 PBGA

CY7C1380C-167BZI

BB165A 165 fBGA

CY7C1382C-167BZI

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.

Operating Range

Commercial

Industrial

Page 32 of 36
Updated Ordering Information
128904 09/11/03
DPM Changed ordering of notes

Updated JTAG Boundary Scan order

Removed Pipelined Read/Write Timing diagram

Added tPOWER specification in Switching Characteristics table
206081 02/13/04

RKF Final Datasheet

Page 36 of 36

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1380C-167BZI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1380C-167BZI 508002