CY7C1370BV25-167AC

CY7C1370BV25-167AC Datasheet

CY7C1372BV25 CY7C1370BV25

Part	Datasheet
CY7C1370BV25-167AC	CY7C1370BV25-167AC (pdf)

PDF Datasheet Preview
CY7C1372BV25 CY7C1370BV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed 200,167, 150, and 133 MHz • Fast access time ns • Internally synchronized registered outputs eliminate the need to control OE • Single 2.5V +5% • Single WE Read/Write control pin • Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications • Interleaved or linear 4-word burst capability • Individual byte Write control may be tied LOW • CEN pin to enable clock and suspend operations • Three chip enables for simple depth expansion • JTAG boundary scan for BGA packaging version • Available in 119-ball bump BGA and 100-pin TQFP packages • Automatic power-down available using zz mode or CE deselect Functional Description The CY7C1370BV25 and CY7C1372BV25 SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency. They integrate 524,288 x 36 and 1,048,576 x 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single layer polysilicon, threelayer metal technology. Each memory cell consists of six transistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous Logic Block Diagram ADV/LD CY7C1370 CY7C1372 X = 18:0 X = 19:0 DQX DPX X = a, b, c, d X = a, b X = a, b, c, d X = a, b BWSX X = a, b, c, d X = a, b Ax CEN CCEE12 CE3 WE BWSx Mode CONTROL and WRITE LOGIC inputs include all addresses, all data inputs, depth-expansion Chip Enables CE1, CE2 and CE3 , cycle start input ADV/LD , Clock Enable CEN , Byte Write Selects BWSa, BWSb, BWSc and BWSd , and Read-Write control WE . BWSc and BWSd apply to CY7C1370BV25 only. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either Read or Write. A Clock Enable CEN pin allows operation of the CY7C1370BV25/CY7C1372BV25 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is HIGH and the internal device registers will hold their previous values. There are three Chip Enable CE1, CE2, CE3 pins that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers Read or Write will be completed. The data bus will be in high-impedance state two cycles after chip is deselected or a Write cycle is initiated. The CY7C1370BV25 and CY7C1372BV25 have an on-chip two-bit burst counter. In the burst mode, the CY7C1370BV25 and CY7C1372BV25 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH Output Enable OE and burst sequence select MODE are the asynchronous signals. OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used. Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. DaDta-In Q REG. OUTOUT REGISTERS and LOGIC 256K x 36/ 512K x 18 MEMORY ARRAY DQx DPx Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Pin Configurations CY7C1372BV25 CY7C1370BV25 Ordering Information Speed MHz Ordering Code CY7C1370BV25-200AC CY7C1372BV25-200AC CY7C1370BV25-200BGC CY7C1372BV25-200BGC CY7C1370BV25-200BZC CY7C1372BV25-200BZC CY7C1370BV25-167AC CY7C1372BV25-167AC CY7C1370BV25-167BGC CY7C1372BV25-167BGC CY7C1370BV25-167BZC CY7C1372BV25-167BZC CY7C1370BV25-150AC CY7C1372BV25-150AC CY7C1370BV25-150BGC CY7C1372BV25-150BGC CY7C1370BV25-150BZC CY7C1372BV25-150BZC CY7C1370BV25-133AC CY7C1372BV25-133AC CY7C1370BV25-133BGC CY7C1372BV25-133BGC CY7C1370BV25-133BZC CY7C1372BV25-133BZC CY7C1370BV25-167AI CY7C1372BV25-167AI CY7C1370BV25-167BGI CY7C1372BV25-167BGI CY7C1370BV25-167BZI CY7C1372BV25-167BZI CY7C1370BV25-150AI CY7C1372BV25-150AI CY7C1370BV25-150BGI CY7C1372BV25-150BGI CY7C1370BV25-150BZI CY7C1372BV25-150BZI CY7C1370BV25-133AI CY7C1372BV25-133AI CY7C1370BV25-133BGI CY7C1372BV25-133BGI CY7C1370BV25-133BZI CY7C1372BV25-133BZI Shaded areas contain advance information. Package Name A101 Package Type 100-Lead Thin Quad Flat Pack BG119 119 BGA BA165A 165 FBGA A101 100-Lead Thin Quad Flat Pack BG119 119 BGA BA165A 165 FBGA A101 100-Lead Thin Quad Flat Pack

PDF Datasheet Preview

CY7C1372BV25 CY7C1370BV25
512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
• Zero Bus Latency, no dead cycles between Write and Read cycles
• Fast clock speed 200,167, 150, and 133 MHz
• Fast access time ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 2.5V +5%
• Single WE Read/Write control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte Write control may be
tied LOW
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA and 100-pin TQFP
packages
• Automatic power-down available using zz mode or CE
deselect

Functional Description

The CY7C1370BV25 and CY7C1372BV25 SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency. They integrate 524,288 x 36 and 1,048,576 x 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single layer polysilicon, threelayer metal technology. Each memory cell consists of six transistors. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous

Logic Block Diagram

ADV/LD

CY7C1370 CY7C1372

X = 18:0

X = 19:0

DQX DPX

X = a, b, c, d X = a, b X = a, b, c, d X = a, b

BWSX X = a, b, c, d X = a, b

Ax CEN

CCEE12 CE3 WE BWSx Mode

CONTROL and WRITE

LOGIC
inputs include all addresses, all data inputs, depth-expansion Chip Enables CE1, CE2 and CE3 , cycle start input ADV/LD , Clock Enable CEN , Byte Write Selects BWSa, BWSb, BWSc and BWSd , and Read-Write control WE . BWSc and BWSd apply to CY7C1370BV25 only.

Address and control signals are applied to the SRAM during one clock cycle, and two cycles later, its associated data occurs, either Read or Write.

A Clock Enable CEN pin allows operation of the CY7C1370BV25/CY7C1372BV25 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is HIGH and the internal device registers will hold their previous values.

There are three Chip Enable CE1, CE2, CE3 pins that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers Read or Write will be completed. The data bus will be in high-impedance state two cycles after chip is deselected or a Write cycle is initiated.

The CY7C1370BV25 and CY7C1372BV25 have an on-chip two-bit burst counter. In the burst mode, the CY7C1370BV25 and CY7C1372BV25 provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address ADV/LD = LOW or increment the internal burst counter ADV/LD = HIGH

Output Enable OE and burst sequence select MODE are the asynchronous signals. OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used.

Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation.

DaDta-In Q

REG.

OUTOUT REGISTERS and LOGIC
256K x 36/ 512K x 18

MEMORY ARRAY

DQx DPx

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current

Pin Configurations

CY7C1372BV25 CY7C1370BV25
Ordering Information

Speed MHz
Ordering Code

CY7C1370BV25-200AC

CY7C1372BV25-200AC

CY7C1370BV25-200BGC CY7C1372BV25-200BGC

CY7C1370BV25-200BZC CY7C1372BV25-200BZC

CY7C1370BV25-167AC

CY7C1372BV25-167AC

CY7C1370BV25-167BGC CY7C1372BV25-167BGC

CY7C1370BV25-167BZC CY7C1372BV25-167BZC

CY7C1370BV25-150AC

CY7C1372BV25-150AC

CY7C1370BV25-150BGC CY7C1372BV25-150BGC

CY7C1370BV25-150BZC CY7C1372BV25-150BZC

CY7C1370BV25-133AC

CY7C1372BV25-133AC

CY7C1370BV25-133BGC CY7C1372BV25-133BGC

CY7C1370BV25-133BZC CY7C1372BV25-133BZC

CY7C1370BV25-167AI

CY7C1372BV25-167AI

CY7C1370BV25-167BGI CY7C1372BV25-167BGI

CY7C1370BV25-167BZI CY7C1372BV25-167BZI

CY7C1370BV25-150AI

CY7C1372BV25-150AI

CY7C1370BV25-150BGI CY7C1372BV25-150BGI

CY7C1370BV25-150BZI CY7C1372BV25-150BZI

CY7C1370BV25-133AI

CY7C1372BV25-133AI

CY7C1370BV25-133BGI CY7C1372BV25-133BGI

CY7C1370BV25-133BZI CY7C1372BV25-133BZI

Shaded areas contain advance information.

Package Name

A101

Package Type 100-Lead Thin Quad Flat Pack

BG119 119 BGA

BA165A 165 FBGA

A101
100-Lead Thin Quad Flat Pack

BG119 119 BGA

BA165A 165 FBGA

A101
100-Lead Thin Quad Flat Pack

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Datasheet ID: CY7C1370BV25-167AC 507995