CY7C1370D-200BGXC

CY7C1370D-200BGXC Datasheet


CY7C1370D, CY7C1372D

Part Datasheet
CY7C1370D-200BGXC CY7C1370D-200BGXC CY7C1370D-200BGXC (pdf)
Related Parts Information
CY7C1372D-167BGC CY7C1372D-167BGC CY7C1372D-167BGC
PDF Datasheet Preview
CY7C1370D, CY7C1372D
18-Mbit 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
• Pin-compatible and Functionally equivalent to ZBT
• Supports 250-MHz Bus Operations with Zero Wait States Available speed grades are 250, 200, and 167 MHz
• Internally Self-timed Output Buffer Control to eliminate the need to use Asynchronous OE
• Fully Registered Inputs and Outputs for Pipelined Operation
• Byte Write capability
• 3.3V core Power Supply VDD
• 3.3V/2.5V I/O Power Supply VDDQ
• Fast Clock-to-Output Times
ns for 250 MHz device
• Clock Enable CEN Pin to suspend operation
• Synchronous Self-timed Writes
• Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 119-Ball BGA and 165-Ball FBGA Package
• IEEE JTAG-Compatible Boundary Scan
• Burst or Interleaved Burst Order
• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370D and CY7C1372D are equipped with the advanced NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370D and CY7C1372D are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects for CY7C1370D and for CY7C1372D and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tristate control. In order to avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence.

Selection Guide

Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
250 MHz 350 70
200 MHz 300 70
167 MHz

Unit
• San Jose, CA 95134-1709
• 408-943-2600
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CY7C1370D, CY7C1372D

Logic Block Diagram-CY7C1370D 512K x 36

A0, A1, A

MODE

ADV/LD

BW a BW b BW c BW d

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC
2.5V TAP AC Test Conditions 14 2.5V TAP AC Output Load Equivalent 14 TAP DC Electrical Characteristics And Operating Conditions 14 Identification Register Definitions 15 Scan Register Sizes 15 Identification Codes 15 119-Ball BGA Boundary Scan Order 16 165-Ball BGA Boundary Scan Order.............................. 17 Maximum Ratings 18 Operating Range 18 Electrical Characteristics 18 Capacitance 19 Thermal 19 Switching Characteristics 20 Switching Waveforms 21 Ordering Information 23 Ordering Information 23 Package Diagrams 24 Document History Page 27 Sales, Solutions, and Legal Information 28

Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28

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Pin Configurations

CY7C1370D, CY7C1372D

Figure 100-Pin TQFP
100 A 99 A 98 CE1 97 CE2 96 BWd 95 BWc 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A 100 A 99 A 98 CE1 97 CE2 96 NC 95 NC 94 BWb 93 BWa 92 CE3 91 VDD 90 VSS 89 CLK 88 WE 87 CEN 86 OE 85 ADV/LD 84 A 83 A 82 A 81 A

DQPc 1

DQc 2

DQc 3 VDDQ 4

VSS 5 DQc 6

DQc 7

DQc 8

DQc 9

VDDQ 11

DQc 12

DQc 13

NC 14

VDD 15

VSS 17

DQd 18

DQd 19 VDDQ 20 VSS 21 DQd 22 DQd 23 DQd 24

DQd 25 VSS 26 VDDQ 27 DQd 28 DQd 29 DQPd 30

CY7C1370D 512K x 36
80 DQPb NC 1
79 DQb NC 2
78 DQb NC 3
77 VDDQ 4
76 VSS

VSS 5
75 DQb NC 6
74 DQb NC 7
73 DQb 8
72 DQb 9
71 70

VDDQ
10 11
69 DQb 12
68 DQb 13
67 VSS NC
66 NC
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative.

Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at
Ordering Information

Speed MHz
Ordering Code CY7C1370D-167AXC CY7C1372D-167AXC CY7C1372D-167BGC CY7C1370D-167BZXC CY7C1370D-167AXI CY7C1372D-167AXI CY7C1370D-200AXC CY7C1372D-200AXC CY7C1370D-200BGXC CY7C1370D-200BZC CY7C1370D-200AXI CY7C1370D-250AXC

Package Diagram 51-85050
51-85115 51-85180 51-85050
51-85050
51-85115 51-85180 51-85050 51-85050

Part and Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
119-ball Grid Array 14 x 22 x mm 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Pb-Free 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free
119-ball Grid Array 14 x 22 x mm Pb-Free 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-Free

Operating Range

Commercial

Industrial Commercial

Industrial Commercial

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CY7C1370D, CY7C1372D

Package Diagrams

Figure 100-Pin Thin Plastic Quad Flatpack 14 X 20 X mm
51-85050 *C

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CY7C1370D, CY7C1372D

Figure 119-Ball BGA 14 X 22 X mm
51-85115*C

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CY7C1370D, CY7C1372D

Figure 165-Ball FBGA 13 X 15 X mm
51-85180 *C

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CY7C1370D, CY7C1372D

Document History Page

Document Title CY7C1372D/CY7C1370D 18-Mbit 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Document Number 38-05555

ECN No.

Submission Date

Orig. of Change

Description of Change
254509

See ECN

RKF New data sheet
276690

See ECN
VBL Changed TQFP pkg to Lead-free TQFP in Ordering Information section

Added comment of Lead-free BG and BZ packages availability
288531

See ECN

SYT Edited description under “IEEE Serial Boundary Scan JTAG ” for
non-compliance with

Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA

Packages
326078

See ECN
PCI Address expansion pins/balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri-State Changed description on the Tap Instruction Set Overview and Extest Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to and °C/W respectively Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to and °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to and °C/W respectively Modified VOL, VOH test conditions Removed shading from AC/DC Table and Selection Guide Removed comment of ‘Lead-free BG packages availability’ below the Ordering Information Updated Ordering Information Table Changed from Preliminary to final
370734

See ECN

PCI Modified test condition in note# 17 from VDDQ < VDD to VDDQ VDD
416321

See ECN

NXR Converted from preliminary to final

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table

Changed three-state to tri-state Changed the IX current values of MODE on page # 18 from µA and 30 µA to µA and 5 µA Changed the IX current values of ZZ on page # 18 from µA and 5 µA to µA and 30 µA
Changed VIH < VDD to VIH < VDDon page # 18 Replaced Package Name column with Package Diagram in the Ordering
Information table Updated Ordering Information Table
475677

See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

AC Switching Characteristics table.
Updated the Ordering Information table.
2756940 08/27/2009

VKN Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information.
2896585 03/21/2010
NJY Removed obsolete parts from Ordering Information table. Updated package
diagram, data sheet template, and Sales, Solutions, and Legal Information
section.

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CY7C1370D, CY7C1372D

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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More datasheets: 61124-350CACLF | 61124-250CACLF | 61124-240CACLF | 61124-240CALF | 61124-251CACLF | 61124-850CALF | 61124-740CALF | RBA-3 | C000064 | CY7C1372D-167BGC


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Datasheet ID: CY7C1370D-200BGXC 507993