CY7C1361B-100BGC

CY7C1361B-100BGC Datasheet


CY7C1361B CY7C1363B

Part Datasheet
CY7C1361B-100BGC CY7C1361B-100BGC CY7C1361B-100BGC (pdf)
Related Parts Information
CY7C1361B-117AJC CY7C1361B-117AJC CY7C1361B-117AJC
CY7C1361B-117AC CY7C1361B-117AC CY7C1361B-117AC
CY7C1361B-100AC CY7C1361B-100AC CY7C1361B-100AC
CY7C1363B-100AC CY7C1363B-100AC CY7C1363B-100AC
PDF Datasheet Preview
CY7C1361B CY7C1363B
9-Mbit 256K x 36/512K x 18 Flow-Through SRAM

Functional Description[1]
• Supports 133-MHz bus operations
• 256K X 36/512K X 18 common I/O
• 3.3V and +10% core power supply VDD
• 2.5V or 3.3V I/O supply VDDQ
• Fast clock-to-output times
ns 133-MHz version
ns 117-MHz version
ns 100-MHz version
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-ball fBGA packages Both 2 and 3 Chip Enable Options for TQFP
• JTAG boundary scan for BGA and fBGA packages
• “ZZ” Sleep Mode option

The CY7C1361B/CY7C1363B is a 3.3V, 256K x 36 and 512K x 18 Synchronous Flow through SRAMs, respectively designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CCoEn1tr o, EW2riatendECnaEb3l[e2]s , BBuWrsxt, and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

The CY7C1361B/CY7C1363B allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

The CY7C1361B/CY7C1363B operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide
133 MHz
117 MHz
100 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Notes For recommendations, please refer to the Cypress application note System Design Guidelines on CE3 is for A version of TQFP 3 Chip Enable Option and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

Unit ns mA

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C1361B CY7C1363B

Logic Block Diagram CY7C1361B 256K x 36

A0, A1, A MODE ADV CLK

ADSC ADSP BWD

BWA BWE

GW CE1 CE2 CE3 OE

ADDRESS REGISTER

A[1:0]

BURST Q1

COUNTER

AND LOGIC

DQD, DQPD BYTE

WRITE REGISTER

DQC, DQPC BYTE

WRITE REGISTER

DQB, DQPB BYTE
Ordering Information

Speed MHz
Ordering Code CY7C1361B-133AC CY7C1363B-133AC CY7C1361B-133AI CY7C1363B-133AI CY7C1361B-133AJC CY7C1363B-133AJC CY7C1361B-133AJI CY7C1363B-133AJI CY7C1361B-133BGC CY7C1363B-133BGC CY7C1361B-133BGI CY7C1363B-133BGI CY7C1361B-133BZC CY7C1363B-133BZC CY7C1361B-133BZI CY7C1363B-133BZI

High-Z

DON’T CARE

Package Name

Part and Package Type

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm 3 Chip Enables

Operating Range

Commercial

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm 3 Chip Enables

Industrial

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm 2 Chip Enables

Commercial

A101 100-lead Thin Quad Flat Pack 14 x 20 x mm 2 Chip Enables

Industrial

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and Commercial JTAG

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

Industrial

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Commercial 3 Chip Enables and JTAG

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Industrial 3 Chip Enables and JTAG

Page 29 of 34

CY7C1361B CY7C1363B
Ordering Information continued

Speed MHz
Ordering Code

Package Name

Part and Package Type
117 CY7C1361B-117AC CY7C1363B-117AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1361B-117AI CY7C1363B-117AI

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1361B-117AJC CY7C1363B-117AJC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables

CY7C1361B-117AJI CY7C1363B-117AJI

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables

CY7C1361B-117BGC CY7C1363B-117BGC

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1361B-117BGI CY7C1363B-117BGI

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1361B-117BZC CY7C1363B-117BZC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

CY7C1361B-117BZI CY7C1363B-117BZI

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG
100 CY7C1361B-100AC CY7C1363B-100AC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1361B-100AI CY7C1363B-100AI

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 3 Chip Enables

CY7C1361B-100AJC CY7C1363B-100AJC

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables

CY7C1361B-100AJI CY7C1363B-100AJI

A101 100-lead Thin Quad Flat Pack 14 x 20 x 1.4mm 2 Chip Enables

CY7C1361B-100BGC CY7C1363B-100BGC

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1361B-100BGI CY7C1363B-100BGI

BG119 119-ball 14 x 22 x mm BGA 3 Chip Enables and JTAG

CY7C1361B-100BZC CY7C1363B-100BGC

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

CY7C1361B-100BZI CY7C1363B-100BGI

BB165A 165-ball Fine-Pitch Ball Grid Array 13 x 15 x 1.2mm 3 Chip Enables and JTAG

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.

Operating Range

Commercial Industrial

Commercial Industrial

Commercial Industrial

Commercial Industrial
VBL Update Ordering Info section unshade active part number

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Datasheet ID: CY7C1361B-100BGC 507989