CY7C1362C-200AXCT

CY7C1362C-200AXCT Datasheet

CY7C1360C, CY7C1362C

Part	Datasheet
CY7C1362C-200AXCT	CY7C1362C-200AXCT (pdf)

PDF Datasheet Preview
CY7C1360C, CY7C1362C 9-Mbit 256 K x 36/512 K x 18 Pipelined SRAM 9-Mbit 256 K x 36/512 K x 18 Pipelined SRAM n Supports bus operation up to 250 MHz n Available speed grades 250, 200, and 166 MHz n Registered inputs and outputs for pipelined operation n V core power supply VDD n V/3.3 V I/O operation VDDQ n Fast clock-to-output times p ns for 250 MHz device n Provide high performance 3-1-1-1 access rate n User selectable burst counter supporting interleaved or linear burst sequences n Separate processor and controller address strobes n Synchronous self-timed writes n Asynchronous output enable n Single cycle chip deselect n Available in Pb-free 100-pin TQFP package, Pb-free and non Pb-free 119-ball BGA package, and 165-ball FBGA package n TQFP available with 3-chip enable and 2-chip enable n IEEE JTAG-compatible boundary scan Functional Description The CY7C1360C/CY7C1362C SRAM[1] integrates 256 K x 36 and 512 K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3[2] , burst control inputs ADSC, ADSP, and ADV , write enables BWX, and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin. Addresses and chip enables are registered at the rising edge of clock when either address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations see “Pin Definitions” on page 8 and “Truth Table” on page 11 for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1360C/CY7C1362C operate from a V core power supply while all outputs may operate with either a or V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram CY7C1362C 512 K x 18 A0, A1, A MODE ADV CLK ADSC ADSP BW A BWE GW CE 1 CE2 CE3 ADDRESS REGISTER 2 A[1:0] BURST Q1 COUNTER AND LOGIC DQ B,DQP B WRITE REGISTER DQ A, DQP A WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE DQ B,DQP B WRITE DRIVER DQ A, DQP A WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS DQs DQP A DQP B INPUT REGISTERS SLEEP CONTROL Notes For best-practices recommendations, refer to the Cypress application note System Design Guidelines on CE3 is for A version of TQFP 3 Chip Enable option and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1360C, CY7C1362C Logic Block Diagram CY7C1360C 256 K x 36 A 0, A1, A TAP DC Electrical Characteristics and Operating Conditions 17 Identification Register Definitions 18 Scan Register Sizes 18 Identification Codes 18 165-ball FBGA Boundary Scan Order 19 119-ball BGA Boundary Scan Order 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 Capacitance 22 Thermal Resistance 22 Switching Characteristics 23 Switching Waveforms 24 Ordering Information 28 Ordering Code Definitions 28 Package Diagrams 29 Acronyms 32 Document Conventions 32 Units of Measure 32 Document History Page 33 Sales, Solutions, and Legal Information 34 Worldwide Sales and Design Support 34 Products 34 PSoC Solutions 34 Page 3 of 34 [+] Feedback CY7C1360C, CY7C1362C Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current 250 MHz 250 40 200 MHz 166 MHz Unit Pin Configurations Figure 100-pin TQFP 3 Chip Enables - A Version ADSP ADSC ADSP ADSC 100 A 100 A DQPC VDDQ VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ DQPD CY7C1360C 256 K x 36 DQPB VDDQ VDDQ VSSQ VSSQ VSSQ VSSQ VDDQ VDDQ VDDQ VDDQ Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 166 CY7C1360C-166AXC CY7C1360C-166AJXC CY7C1362C-166AJXC CY7C1360C-166BZC CY7C1360C-166AXI 200 CY7C1360C-200AXC CY7C1360C-200AJXC CY7C1360C-200BGC Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 3 chip enable 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 2 chip enable 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 3 chip enable 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 3 chip enable 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 2 chip enable 51-85115 119-ball Grid Array 14 x 22 x mm Operating Range Commercial Industrial Commercial Ordering Code Definitions CY7C 13XX C - XXX X Temperature range X = C or I C = Commercial I = Industrial Package Type XXX = AX or AJX or BZ or BG AX = 100-pin TQFP Pb-free 3 chip enable AJX = 100-pin TQFP Pb-free 2 chip enable BZ = 165-ball FPBGA BG = 119-ball BGA Speed Grade 166 MHz / 200 MHz Process Technology 90 nm 13XX = 1360 or 1362 1360 = SCD, 256 K x 36 9 Mb 1362 = SCD, 512 K x 18 9 Mb CY7C = Cypress SRAMs Page 28 of 34 [+] Feedback CY7C1360C, CY7C1362C Package Diagrams Figure 100-pin Thin Plastic Quad Flatpack 14 x 20 x mm 51-85050 C Page 29 of 34 [+] Feedback CY7C1360C, CY7C1362C Figure 119-ball PBGA 14 x 22 x mm 51-85115 C Page 30 of 34 [+] Feedback CY7C1360C, CY7C1362C Figure 165-ball FBGA 13 x 15 x mm 51-85180 *C Page 31 of 34 [+] Feedback Acronyms Acronym BGA CE CEN FPBGA I/O JTAG OE SRAM TCK TMS TDI TDO TQFP WE Description ball grid array chip enable clock enable fine-pitch ball grid array input/output Joint Test Action Group output enable static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable CY7C1360C, CY7C1362C Document Conventions Units of Measure Symbol ns V µA mA ms MHz pF W °C Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds Mega Hertz pico Farad Watts degree Celcius Page 32 of 34 [+] Feedback CY7C1360C, CY7C1362C Document History Page Document Title CY7C1360C/CY7C1362C 9-Mbit 256 K x 36/512 K x 18 Pipelined SRAM Document Number 38-05540 ECN NO. Submission Date Orig. of Change Description of Change 241690 See ECN RKF New data sheet 278130 See ECN Changed TQFP pkg to Lead-free TQFP in Ordering Information section Added comment of Lead-free BG and BZ packages availability 248929 See ECN VBL Changed ISB1 and ISB3 from DC Characteristics table as follows: ISB1 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA ISB3 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA Changed IDDZZ to 50 mA Added BG and BZ pkg lead-free part numbers to ordering info section 323636 See ECN PCI Changed frequency of 225 MHz into 250 MHz Added tCYC of ns for 250 MHz Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to and °C/W respectively Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to and °C/W respectively Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to and °C/W respectively Modified address expansion as per JEDEC Standard Removed comment of Lead-free BG and BZ packages availability 332879 See ECN PCI Unshaded 200 and 166 MHz speed bins in the AC/DC Table and Selection Guide Added Address Expansion pins in the Pin Definition Table Changed Device Width 23:18 for 119-BGA from to 101000 Added separate row for 165 -FBGA Device Width 23:18 Modified VOL, VOH test conditions Updated Ordering Information Table 357258 See ECN PCI Changed from Preliminary to Final Removed Shading on 250MHz Speed Bin in Selection Guide and AC/DC Table Changed ISB2 from 30 to 40 mA Updated Ordering Information Table 377095 See ECN PCI Modified test condition in note# 16 from VDDQ < VDD to VDDQ VDD 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed three-state to tri-state on page# 9 & page# 10 Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Page 33 of 34 [+] Feedback CY7C1360C, CY7C1362C Document History Page continued Document Title CY7C1360C/CY7C1362C 9-Mbit 256 K x 36/512 K x 18 Pipelined SRAM Document Number 38-05540 ECN NO. Submission Date Orig. of Change Description of Change 2756340 08/26/2009 VKN/AESA Updated template Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. 3046851 10/04/2010 NJY Added Ordering Code Definitions. Updated Package Diagrams. Added Acronyms and Units of Measure. Minor edits and updated in new template. 3052882 10/11/2010 NJY Removed obsolete part. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 34 of 34 [+] Feedback

PDF Datasheet Preview

CY7C1360C, CY7C1362C
9-Mbit 256 K x 36/512 K x 18 Pipelined SRAM
9-Mbit 256 K x 36/512 K x 18 Pipelined SRAM
n Supports bus operation up to 250 MHz n Available speed grades 250, 200, and 166 MHz n Registered inputs and outputs for pipelined operation n V core power supply VDD n V/3.3 V I/O operation VDDQ n Fast clock-to-output times
p ns for 250 MHz device n Provide high performance 3-1-1-1 access rate n User selectable burst counter supporting
interleaved or linear burst sequences n Separate processor and controller address strobes n Synchronous self-timed writes n Asynchronous output enable n Single cycle chip deselect n Available in Pb-free 100-pin TQFP package, Pb-free and non

Pb-free 119-ball BGA package, and 165-ball FBGA package n TQFP available with 3-chip enable and 2-chip enable n IEEE JTAG-compatible boundary scan

Functional Description

The CY7C1360C/CY7C1362C SRAM[1] integrates 256 K x 36 and 512 K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable CE1 , depth-expansion chip enables CE2 and CE3[2] , burst control inputs ADSC, ADSP, and ADV , write enables BWX, and BWE , and global write GW . Asynchronous inputs include the output enable OE and the ZZ pin.

Addresses and chip enables are registered at the rising edge of clock when either address strobe processor ADSP or address strobe controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle.This part supports byte write operations see “Pin Definitions” on page 8 and “Truth Table” on page 11 for further details . Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1360C/CY7C1362C operate from a V core power supply while all outputs may operate with either a or V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Logic Block Diagram CY7C1362C 512 K x 18

A0, A1, A

MODE ADV CLK

ADSC ADSP

BW A BWE GW CE 1 CE2 CE3

ADDRESS REGISTER
2 A[1:0]

BURST Q1 COUNTER AND

LOGIC

DQ B,DQP B WRITE REGISTER

DQ A, DQP A WRITE REGISTER

ENABLE REGISTER

PIPELINED ENABLE

DQ B,DQP B WRITE DRIVER

DQ A, DQP A WRITE DRIVER

MEMORY ARRAY

SENSE AMPS

OUTPUT REGISTERS

OUTPUT BUFFERS

DQs DQP A DQP B

INPUT REGISTERS

SLEEP

CONTROL

Notes For best-practices recommendations, refer to the Cypress application note System Design Guidelines on CE3 is for A version of TQFP 3 Chip Enable option and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1360C, CY7C1362C

Logic Block Diagram CY7C1360C 256 K x 36

A 0, A1, A
TAP DC Electrical Characteristics and Operating Conditions 17 Identification Register Definitions 18 Scan Register Sizes 18 Identification Codes 18 165-ball FBGA Boundary Scan Order 19 119-ball BGA Boundary Scan Order 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 Capacitance 22 Thermal Resistance 22 Switching Characteristics 23 Switching Waveforms 24 Ordering Information 28
Ordering Code Definitions 28 Package Diagrams 29 Acronyms 32 Document Conventions 32

Units of Measure 32 Document History Page 33 Sales, Solutions, and Legal Information 34

Worldwide Sales and Design Support 34 Products 34 PSoC Solutions 34

Page 3 of 34 [+] Feedback

CY7C1360C, CY7C1362C

Selection Guide

Description Maximum access time Maximum operating current Maximum CMOS standby current
250 MHz 250 40
200 MHz
166 MHz

Unit

Pin Configurations

Figure 100-pin TQFP 3 Chip Enables - A Version

ADSP

ADSC

ADSP

ADSC
100 A
100 A

DQPC

VDDQ

VSSQ

VSSQ

VDDQ

VDDQ

VSSQ

VSSQ

VDDQ

DQPD

CY7C1360C 256 K x 36

DQPB

VDDQ

VDDQ

VSSQ

VSSQ

VSSQ

VSSQ

VDDQ

VDDQ

VDDQ

VDDQ
Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
166 CY7C1360C-166AXC

CY7C1360C-166AJXC CY7C1362C-166AJXC CY7C1360C-166BZC CY7C1360C-166AXI
200 CY7C1360C-200AXC

CY7C1360C-200AJXC

CY7C1360C-200BGC

Package Diagram

Part and Package Type
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 3 chip enable
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 2 chip enable
51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 3 chip enable
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 3 chip enable
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Pb-free 2 chip enable
51-85115 119-ball Grid Array 14 x 22 x mm

Operating Range

Commercial

Industrial Commercial
Ordering Code Definitions CY7C 13XX C - XXX X

Temperature range X = C or I C = Commercial I = Industrial

Package Type XXX = AX or AJX or BZ or BG AX = 100-pin TQFP Pb-free 3 chip enable AJX = 100-pin TQFP Pb-free 2 chip enable BZ = 165-ball FPBGA BG = 119-ball BGA

Speed Grade 166 MHz / 200 MHz

Process Technology 90 nm
13XX = 1360 or 1362 1360 = SCD, 256 K x 36 9 Mb 1362 = SCD, 512 K x 18 9 Mb

CY7C = Cypress SRAMs

Page 28 of 34 [+] Feedback

CY7C1360C, CY7C1362C

Package Diagrams

Figure 100-pin Thin Plastic Quad Flatpack 14 x 20 x mm
51-85050 *C

Page 29 of 34 [+] Feedback

CY7C1360C, CY7C1362C

Figure 119-ball PBGA 14 x 22 x mm
51-85115 *C

Page 30 of 34 [+] Feedback

CY7C1360C, CY7C1362C

Figure 165-ball FBGA 13 x 15 x mm
51-85180 *C

Page 31 of 34 [+] Feedback

Acronyms

Acronym BGA CE CEN FPBGA I/O JTAG OE SRAM TCK TMS TDI TDO TQFP WE

Description ball grid array chip enable clock enable fine-pitch ball grid array input/output Joint Test Action Group output enable static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable

CY7C1360C, CY7C1362C

Document Conventions

Units of Measure

Symbol ns V µA mA ms MHz pF W °C

Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds Mega Hertz pico Farad Watts degree Celcius

Page 32 of 34 [+] Feedback

CY7C1360C, CY7C1362C

Document History Page

Document Title CY7C1360C/CY7C1362C 9-Mbit 256 K x 36/512 K x 18 Pipelined SRAM Document Number 38-05540

ECN NO.

Submission Date

Orig. of Change

Description of Change
241690 See ECN

RKF New data sheet
278130 See ECN
Changed TQFP pkg to Lead-free TQFP in Ordering Information section

Added comment of Lead-free BG and BZ packages availability
248929 See ECN

VBL Changed ISB1 and ISB3 from DC Characteristics table as follows:

ISB1 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA

ISB3 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA

Changed IDDZZ to 50 mA
Added BG and BZ pkg lead-free part numbers to ordering info section
323636 See ECN

PCI Changed frequency of 225 MHz into 250 MHz

Added tCYC of ns for 250 MHz Changed ΘJA and ΘJC for TQFP Package from 25 and 9 °C/W to and °C/W respectively

Changed ΘJA and ΘJC for BGA Package from 25 and 6 °C/W to and °C/W respectively

Changed ΘJA and ΘJC for FBGA Package from 27 and 6 °C/W to and °C/W respectively

Modified address expansion as per JEDEC Standard

Removed comment of Lead-free BG and BZ packages availability
332879 See ECN

PCI Unshaded 200 and 166 MHz speed bins in the AC/DC Table and Selection

Guide

Added Address Expansion pins in the Pin Definition Table

Changed Device Width 23:18 for 119-BGA from to 101000

Added separate row for 165 -FBGA Device Width 23:18
Modified VOL, VOH test conditions Updated Ordering Information Table
357258 See ECN

PCI Changed from Preliminary to Final

Removed Shading on 250MHz Speed Bin in Selection Guide and AC/DC

Table
Changed ISB2 from 30 to 40 mA Updated Ordering Information Table
377095 See ECN

PCI Modified test condition in note# 16 from VDDQ < VDD to VDDQ VDD
408298 See ECN

RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court” Changed three-state to tri-state on page# 9 & page# 10

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering

Information table
Updated Ordering Information Table
501793 See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

AC Switching Characteristics table.
Updated the Ordering Information table.

Page 33 of 34 [+] Feedback

CY7C1360C, CY7C1362C

Document History Page continued

Document Title CY7C1360C/CY7C1362C 9-Mbit 256 K x 36/512 K x 18 Pipelined SRAM Document Number 38-05540

ECN NO.

Submission Date

Orig. of Change

Description of Change
2756340 08/26/2009 VKN/AESA Updated template

Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information.
3046851 10/04/2010
NJY Added Ordering Code Definitions.

Updated Package Diagrams.

Added Acronyms and Units of Measure.

Minor edits and updated in new template.
3052882 10/11/2010

NJY Removed obsolete part.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.

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More datasheets: 3133 GY001 | 3134 BR005 | 3135 BK005 | 3135 BR005 | 3135 GY005 | 3133 BK001 | 3133 BL001 | 3133 BR001 | 76000775 | 161A17539X

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1362C-200AXCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1362C-200AXCT 507985