CY7C1357C-100AXCT

CY7C1357C-100AXCT Datasheet

CY7C1355C CY7C1357C

Part	Datasheet
CY7C1357C-100AXCT	CY7C1357C-100AXCT (pdf)

Related Parts	Information
CY7C1355C-100AXC	CY7C1355C-100AXC
CY7C1355C-100BGC	CY7C1355C-100BGC
CY7C1355C-100BGCT	CY7C1355C-100BGCT
CY7C1355C-133BGC	CY7C1355C-133BGC
CY7C1355C-133BGXC	CY7C1355C-133BGXC
CY7C1355C-133BGCT	CY7C1355C-133BGCT
CY7C1357C-100AXC	CY7C1357C-100AXC
CY7C1357C-133AXIT	CY7C1357C-133AXIT
CY7C1357C-133AXI	CY7C1357C-133AXI
CY7C1355C-100AXCT	CY7C1355C-100AXCT

PDF Datasheet Preview
CY7C1355C CY7C1357C 9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] • No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 3.3V/2.5V I/O power supply VDDQ • Fast clock-to-output times ns for 133-MHz device • Clock Enable CEN pin to enable clock and suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • Available in JEDEC-standard and lead-free 100-Pin TQFP, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package • Three chip enables for simple depth expansion. • Automatic Power-down feature available using ZZ mode or CE deselect • IEEE JTAG-Compatible Boundary Scan • Burst or interleaved burst order • Low standby power The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device . Write operations are controlled by the two or four Byte Write Select BWX and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 133 MHz 250 40 100 MHz 180 40 Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Unit ns mA Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1355C 256K x 36 A0, A1, A MODE ADDRESS REGISTER A1 A0 D1 D0 ADV/LD C WRITE ADDRESS REGISTER Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 133 CY7C1355C-133AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1357C-133AXC CY7C1355C-133BGC 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1357C-133BGC CY7C1355C-133BGXC 51-85115 119-ball Grid Array 14 x 22 x mm Lead-Free CY7C1357C-133BGXC CY7C1355C-133BZC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm CY7C1357C-133BZC CY7C1355C-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1357C-133BZXC CY7C1355C-133AXI 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free lndustrial CY7C1357C-133AXI CY7C1355C-133BGI 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1357C-133BGI CY7C1355C-133BGXI 51-85115 119-ball Grid Array 14 x 22 x mm Lead-Free CY7C1357C-133BGXI CY7C1355C-133BZI 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm CY7C1357C-133BZI CY7C1355C-133BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1357C-133BZXI 100 CY7C1355C-100AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1357C-100AXC CY7C1355C-100BGC 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1357C-100BGC CY7C1355C-100BGXC 51-85115 119-ball Grid Array 14 x 22 x mm Lead-Free CY7C1357C-100BGXC CY7C1355C-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm CY7C1357C-100BZC CY7C1355C-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1357C-100BZXC CY7C1355C-100AXI Updated Ordering Information Table Changed from Preliminary to Final 351895 See ECN PCI Changed ISB2 from 30 to 40 mA Updated Ordering Information Table 377095 See ECN PCI Modified test condition in note# 14 from VIH < VDD to VIH < VDD 408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Changed three-state to tri-state Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table 501793 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table. Updated the Ordering Information table. Page 28 of 28 [+] Feedback

PDF Datasheet Preview

CY7C1355C CY7C1357C
9-Mbit 256K x 36/512K x 18 Flow-Through SRAM with NoBL Architecture

Functional Description[1]
• No Bus Latency NoBL architecture eliminates dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero wait states

Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply VDDQ
• Fast clock-to-output times
ns for 133-MHz device
• Clock Enable CEN pin to enable clock and suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard and lead-free 100-Pin TQFP, lead-free and non lead-free 119-Ball BGA package and 165-Ball FBGA package
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ mode or CE deselect
• IEEE JTAG-Compatible Boundary Scan
• Burst or interleaved burst order
• Low standby power

The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device .

Write operations are controlled by the two or four Byte Write Select BWX and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
133 MHz 250 40
100 MHz 180 40

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on

Unit ns mA

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1355C 256K x 36

A0, A1, A

MODE

ADDRESS REGISTER

A1 A0

D1 D0

ADV/LD C

WRITE ADDRESS REGISTER
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Part and Package Type

Operating Range
133 CY7C1355C-133AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1357C-133AXC

CY7C1355C-133BGC 51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1357C-133BGC

CY7C1355C-133BGXC 51-85115 119-ball Grid Array 14 x 22 x mm Lead-Free

CY7C1357C-133BGXC

CY7C1355C-133BZC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm

CY7C1357C-133BZC

CY7C1355C-133BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1357C-133BZXC

CY7C1355C-133AXI
51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
lndustrial

CY7C1357C-133AXI

CY7C1355C-133BGI
51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1357C-133BGI

CY7C1355C-133BGXI 51-85115 119-ball Grid Array 14 x 22 x mm Lead-Free

CY7C1357C-133BGXI

CY7C1355C-133BZI
51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm

CY7C1357C-133BZI

CY7C1355C-133BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1357C-133BZXI
100 CY7C1355C-100AXC 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Commercial

CY7C1357C-100AXC

CY7C1355C-100BGC 51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1357C-100BGC

CY7C1355C-100BGXC 51-85115 119-ball Grid Array 14 x 22 x mm Lead-Free

CY7C1357C-100BGXC

CY7C1355C-100BZC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm

CY7C1357C-100BZC

CY7C1355C-100BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1357C-100BZXC

CY7C1355C-100AXI
Updated Ordering Information Table

Changed from Preliminary to Final
351895 See ECN

PCI Changed ISB2 from 30 to 40 mA
Updated Ordering Information Table
377095 See ECN

PCI Modified test condition in note# 14 from VIH < VDD to VIH < VDD
408298 See ECN RXU Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table

Changed three-state to tri-state
Replaced Package Name column with Package Diagram in the Ordering

Information table
Updated Ordering Information Table
501793

See ECN

VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC

Switching Characteristics table.
Updated the Ordering Information table.

Page 28 of 28 [+] Feedback

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Datasheet ID: CY7C1357C-100AXCT 507983