CY7C1353F-100AC

CY7C1353F-100AC Datasheet

CY7C1353F

Part	Datasheet
CY7C1353F-100AC	CY7C1353F-100AC (pdf)

PDF Datasheet Preview
CY7C1353F 4-Mb 256K x 18 Flow-through SRAM with NoBL Architecture • Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 256K x 18 common I/O architecture • 2.5V / 3.3V I/O power supply • Fast clock-to-output times ns for 133-MHz device ns for 117-MHz device ns for 100-MHz device ns for 66-MHz device • Clock Enable CEN pin to suspend operation • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100 TQFP package Logic Block Diagram • Burst or interleaved burst order • Low standby power Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device . Write operations are controlled by the two Byte Write Select BW[A:B] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. A0, A1, A MODE ADV/LD BWA BWB ADDRESS REGISTER A1 A0 D1 D0 ADV/LD C WRITE ADDRESS REGISTER Q1 Q0 A1' A0' BURST LOGIC WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY WRITE ARRAY DRIVERS DQs DQPA DQPB OE CE1 CE2 CE3 ZZ READ LOGIC SLEEP CONTROL INPUT E REGISTER Note For recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 CY7C1353F Ordering Information Speed MHz Ordering Code Package Name Package Type 133 CY7C1353F-133AC A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack 133 CY7C1353F-133AI A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack 117 CY7C1353F-117AC A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack 117 CY7C1353F-117AI A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100 CY7C1353F-100AC A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack 100 CY7C1353F-100AI A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack CY7C1353F- 66AC A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack CY7C1353F- 66AI A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack Shaded areas contain advance information. Please contain your local sales representative for more information on ordering these parts. Package Diagrams 100-lead Thin Plastic Quad Flatpack 14 x 20 x mm A101 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 51-85050-*A ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Page 12 of 13 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1353F Document History Page Document Title CY7C1353F 4-Mb 256K x 18 Flow-through SRAM with NoBL Architecture Document Number 38-05212 Orig. of ECN NO. Issue Date Change Description of Change 119830 01/06/03 HGK New Data Sheet 123847 01/18/03 AJH Added power-up requirements to AC test loads and waveforms information 200664 See ECN REF Final Data Sheet Page 13 of 13

PDF Datasheet Preview

CY7C1353F
4-Mb 256K x 18 Flow-through SRAM with NoBL Architecture
• Can support up to 133-MHz bus operations with zero wait states Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 256K x 18 common I/O architecture
• 2.5V / 3.3V I/O power supply
• Fast clock-to-output times
ns for 133-MHz device ns for 117-MHz device ns for 100-MHz device ns for 66-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100 TQFP package

Logic Block Diagram
• Burst or interleaved burst order
• Low standby power

Functional Description[1]

The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 133-MHz device .

Write operations are controlled by the two Byte Write Select BW[A:B] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

A0, A1, A

MODE

ADV/LD BWA BWB

ADDRESS REGISTER

A1 A0

D1 D0

ADV/LD C

WRITE ADDRESS REGISTER

Q1 Q0

A1' A0'

BURST

LOGIC

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

MEMORY

WRITE

ARRAY

DRIVERS

DQs DQPA DQPB

OE CE1 CE2 CE3 ZZ

READ LOGIC

SLEEP CONTROL

INPUT E REGISTER

Note For recommendations, please refer to the Cypress application note System Design Guidelines on

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY7C1353F
Ordering Information

Speed MHz
Ordering Code

Package Name

Package Type
133 CY7C1353F-133AC

A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack
133 CY7C1353F-133AI

A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack
117 CY7C1353F-117AC

A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack
117 CY7C1353F-117AI

A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack
100 CY7C1353F-100AC

A101
100-Lead 14 x 20 x mm Thin Quad Flat Pack
100 CY7C1353F-100AI

A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack

CY7C1353F- 66AC

A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack

CY7C1353F- 66AI

A101 100-Lead 14 x 20 x mm Thin Quad Flat Pack
Shaded areas contain advance information. Please contain your local sales representative for more information on ordering these parts.

Package Diagrams
100-lead Thin Plastic Quad Flatpack 14 x 20 x mm A101

Operating Range

Commercial Industrial

Commercial Industrial

Commercial Industrial

Commercial Industrial
51-85050-*A

ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 12 of 13

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1353F

Document History Page

Document Title CY7C1353F 4-Mb 256K x 18 Flow-through SRAM with NoBL Architecture Document Number 38-05212

Orig. of ECN NO. Issue Date Change

Description of Change
119830 01/06/03 HGK

New Data Sheet
123847 01/18/03

AJH Added power-up requirements to AC test loads and waveforms information
200664 See ECN REF

Final Data Sheet

Page 13 of 13

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Datasheet ID: CY7C1353F-100AC 507981