CY7C1350G-166AXI

CY7C1350G-166AXI Datasheet

CY7C1350G

Part	Datasheet
CY7C1350G-166AXI	CY7C1350G-166AXI (pdf)

PDF Datasheet Preview
CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Functional Description[1] • Pin compatible and functionally equivalent to ZBT devices • Internally self-timed output buffer control to eliminate the need to use OE • Byte Write capability • 128K x 36 common I/O architecture • 3.3V power supply VDD • 2.5V/3.3V I/O power supply VDDQ • Fast clock-to-output times ns for 250-MHz device • Clock Enable CEN pin to suspend operation • Synchronous self-timed writes • Asynchronous output enable OE • Available in lead-free 100-Pin TQFP package, lead-free and non-lead-free 119-Ball BGA package • Burst or interleaved burst order • “ZZ” Sleep mode option Logic Block Diagram The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 250-MHz device Write operations are controlled by the four Byte Write Select BW[A:D] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. CLK CEN A0, A1, A MODE C ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 A1 D1 Q1 A1' A0 D0 BURST Q0 A0' LOGIC ADV/LD WRITE ADDRESS REGISTER 2 ADV/LD BWA BWB BWC BWD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY O U T P U T R E G I S T E R S E D A T A S T E R I N O U T P U T B U F E R S E DQs DQPA DQPB DQPC DQPD INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 READ LOGIC SLEEP CONTROL Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 133 CY7C1350G-133AXC CY7C1350G-133AXI 166 CY7C1350G-166AXI 200 CY7C1350G-200AXC CY7C1350G-200AXI Package Diagrams Package Diagram Package Type 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 100-Pin TQFP 14 x 20 x mm 51-85050 Operating Range Commercial Industrial Commercial Industrial 51-85050-C Page 12 of 14 [+] Feedback Package Diagrams continued 119-Ball BGA 14 x 22 x mm 51-85115 CY7C1350G 51-85115-C ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Page 13 of 14 [+] Feedback CY7C1350G Document History Page Document Title CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Document Number 38-05524 Orig. of ECN NO. Issue Date Change Description of Change 224380 See ECN RKF New data sheet 276690 See ECN VBL Changed TQFP pkg to lead-free TQFP in Ordering Info section Added comment of BG lead-free package availability 332895 See ECN SYT Converted from Preliminary to Final Removed 225 MHz and 100 MHz speed grades Address Expansion balls in the pinouts for 119 BGA Package was modified as per JEDEC standards Modified VOL, VOH test conditions Replaced TBDs for ΘJA and ΘJC to their respective values on the Thermal Resistance table Changed the package name for 100 TQFP from A100RA to A101 Removed comment on the availability of BG lead-free package Updated Ordering Information by removing Shaded Parts 351194 See ECN PCI Updated Ordering Information Table D 419264 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Modified test condition from VDDQ < VDD to VDDQ < VDD Modified test condition from VIH < VDD to VIH < VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from A to B Updated the Ordering Information 419705 See ECN RXU Added 100 MHz speed grade 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Updated the Ordering Information table. G 2896584 03/20/2010 NJY Removed obsolete part numbers from Ordering Information table and updated package diagrams. Page 14 of 14 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback

PDF Datasheet Preview

CY7C1350G
4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture

Functional Description[1]
• Pin compatible and functionally equivalent to ZBT devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte Write capability
• 128K x 36 common I/O architecture
• 3.3V power supply VDD
• 2.5V/3.3V I/O power supply VDDQ
• Fast clock-to-output times
ns for 250-MHz device
• Clock Enable CEN pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable OE
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• Burst or interleaved burst order
• “ZZ” Sleep mode option

Logic Block Diagram

The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable CEN signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is ns 250-MHz device

Write operations are controlled by the four Byte Write Select BW[A:D] and a Write Enable WE input. All writes are conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

CLK CEN

A0, A1, A

MODE C

ADDRESS REGISTER 0

WRITE ADDRESS REGISTER 1

A1 D1

Q1 A1'

A0 D0 BURST Q0 A0'

LOGIC

ADV/LD

WRITE ADDRESS REGISTER 2

ADV/LD

BWA BWB BWC BWD

WRITE REGISTRY AND DATA COHERENCY

CONTROL LOGIC

WRITE DRIVERS

MEMORY

ARRAY

O U T P U T R E G I S T E R S E

D A T A S T E R I N

O U T P U T

B U F E R S E

DQs DQPA DQPB DQPC DQPD

INPUT REGISTER 1 E

INPUT REGISTER 0 E

OE CE1 CE2 CE3

READ LOGIC

SLEEP CONTROL
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
133 CY7C1350G-133AXC

CY7C1350G-133AXI
166 CY7C1350G-166AXI
200 CY7C1350G-200AXC

CY7C1350G-200AXI

Package Diagrams

Package Diagram

Package Type
51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
51-85050 100-Pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free
100-Pin TQFP 14 x 20 x mm 51-85050

Operating Range

Commercial Industrial

Commercial Industrial
51-85050-*C

Page 12 of 14 [+] Feedback

Package Diagrams continued
119-Ball BGA 14 x 22 x mm 51-85115

CY7C1350G
51-85115-*C

ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 13 of 14 [+] Feedback

CY7C1350G

Document History Page

Document Title CY7C1350G 4-Mbit 128K x 36 Pipelined SRAM with NoBL Architecture Document Number 38-05524

Orig. of ECN NO. Issue Date Change Description of Change
224380 See ECN RKF New data sheet
276690 See ECN VBL Changed TQFP pkg to lead-free TQFP in Ordering Info section

Added comment of BG lead-free package availability
332895 See ECN SYT Converted from Preliminary to Final

Removed 225 MHz and 100 MHz speed grades

Address Expansion balls in the pinouts for 119 BGA Package was modified as per

JEDEC standards

Modified VOL, VOH test conditions Replaced TBDs for ΘJA and ΘJC to their respective values on the Thermal Resistance table

Changed the package name for 100 TQFP from A100RA to A101

Removed comment on the availability of BG lead-free package
Updated Ordering Information by removing Shaded Parts
351194 See ECN PCI Updated Ordering Information Table
*D 419264 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Modified test condition from VDDQ < VDD to VDDQ < VDD Modified test condition from VIH < VDD to VIH < VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from *A to *B Updated the Ordering Information
419705 See ECN RXU Added 100 MHz speed grade
480368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Updated the Ordering Information table.
*G 2896584 03/20/2010 NJY Removed obsolete part numbers from Ordering Information table and updated package diagrams.

Page 14 of 14

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Datasheet ID: CY7C1350G-166AXI 507976