CY7C1339G-133AXET

CY7C1339G-133AXET Datasheet

CY7C1339G

Part	Datasheet
CY7C1339G-133AXET	CY7C1339G-133AXET (pdf)

Related Parts	Information
CY7C1339G-133AXI	CY7C1339G-133AXI
CY7C1339G-133AXE	CY7C1339G-133AXE
CY7C1339G-133AXIT	CY7C1339G-133AXIT

PDF Datasheet Preview
CY7C1339G 4-Mbit 128K x 32 Pipelined Sync SRAM • Registered inputs and outputs for pipelined operation • 128K x 32 common I/O architecture • 3.3V core power supply VDD • 2.5V/3.3V I/O power supply VDDQ • Fast clock-to-output times ns for 250-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Available in lead-free 100-Pin TQFP package, lead-free and non-lead-free 119-Ball BGA package • “ZZ” Sleep Mode Option Logic Block Diagram Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BW[A:D], and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The CY7C1339G operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. A0, A1, A M ODE ADV CLK A DSC A DSP BW A BW E GW CE1 CE2 CE3 OE A DDR E SS REGISTER A [1:0] Q1 BURST COUNTER CLR AND Q0 LOGIC DQD BYTE W RITE REGISTER DQC BYTE W RITE REGISTER DQB BYTE W RITE REGISTER DQA BYTE W RITE REGISTER ENA BLE REGISTER PIPELINED ENA BLE DQD BYTE WRITE DRIVER DQC BYTE WRITE DRIVER DQB BYTE WRITE DRIVER DQA BYTE WRITE DRIVER M EM ORY ARRAY SENSE AM PS OUTPUT REGISTERS OUTPUT BUFFERS INPUT REGISTERS SLEEP CONTROL Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Selection Guide Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 133 CY7C1339G-133AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1339G-133BGC 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1339G-133BGXC 119-ball Grid Array 14 x 22 x mm Lead-Free CY7C1339G-133AXI 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial CY7C1339G-133BGI 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1339G-133BGXI 119-ball Grid Array 14 x 22 x mm Lead-Free CY7C1339G-133AXE 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Automotive 166 CY7C1339G-166AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1339G-166BGC 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1339G-166BGXC 119-ball Grid Array 14 x 22 x mm Lead-Free CY7C1339G-166AXI 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial CY7C1339G-166BGI 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1339G-166BGXI 119-ball Grid Array 14 x 22 x mm Lead-Free 200 CY7C1339G-200AXC 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial CY7C1339G-200BGC 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1339G-200BGXC 119-ball Grid Array 14 x 22 x mm Lead-Free CY7C1339G-200AXI 51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial CY7C1339G-200BGI 51-85115 119-ball Grid Array 14 x 22 x mm CY7C1339G-200BGXI 288909 See ECN VBL In Ordering Info section, Changed TQFP to PB-free TQFP Added PB-free BG package 332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBDs for ΘJA and ΘJC to their respective values on the Thermal Resistance table Updated the Ordering Information by shading and unshading MPNs as per availability 351194 See ECN PCI Updated Ordering Information Table 366728 See ECN PCI Added VDD/VDDQ test conditions in DC Table Modified test condition in note# 10 from VIH < VDD to VIH < VDD 420883 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51-85050 from A to B Added Automotive Range in Operating Range Table Updated the Ordering Information 480368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Updated the Ordering Information table. Page 18 of 18 [+] Feedback

PDF Datasheet Preview

CY7C1339G
4-Mbit 128K x 32 Pipelined Sync SRAM
• Registered inputs and outputs for pipelined operation
• 128K x 32 common I/O architecture
• 3.3V core power supply VDD
• 2.5V/3.3V I/O power supply VDDQ
• Fast clock-to-output times
ns for 250-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• “ZZ” Sleep Mode Option

Logic Block Diagram

Functional Description[1]

The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BW[A:D], and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1339G operates from a +3.3V core power supply while all outputs may operate with either a or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

A0, A1, A

M ODE ADV CLK

A DSC A DSP

BW A BW E GW

CE1 CE2 CE3 OE

A DDR E SS REGISTER

A [1:0]

Q1 BURST COUNTER CLR AND Q0 LOGIC

DQD BYTE W RITE REGISTER

DQC BYTE W RITE REGISTER

DQB BYTE W RITE REGISTER

DQA BYTE W RITE REGISTER

ENA BLE REGISTER

PIPELINED ENA BLE

DQD BYTE WRITE DRIVER

DQC BYTE WRITE DRIVER

DQB BYTE WRITE DRIVER

DQA BYTE WRITE DRIVER

M EM ORY ARRAY

SENSE AM PS

OUTPUT REGISTERS

OUTPUT BUFFERS

INPUT REGISTERS

SLEEP

CONTROL

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Selection Guide
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
133 CY7C1339G-133AXC
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial

CY7C1339G-133BGC
51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1339G-133BGXC
119-ball Grid Array 14 x 22 x mm Lead-Free

CY7C1339G-133AXI
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial

CY7C1339G-133BGI
51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1339G-133BGXI
119-ball Grid Array 14 x 22 x mm Lead-Free

CY7C1339G-133AXE
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Automotive
166 CY7C1339G-166AXC
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial

CY7C1339G-166BGC
51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1339G-166BGXC
119-ball Grid Array 14 x 22 x mm Lead-Free

CY7C1339G-166AXI
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial

CY7C1339G-166BGI
51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1339G-166BGXI
119-ball Grid Array 14 x 22 x mm Lead-Free
200 CY7C1339G-200AXC
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Commercial

CY7C1339G-200BGC
51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1339G-200BGXC
119-ball Grid Array 14 x 22 x mm Lead-Free

CY7C1339G-200AXI
51-85050 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Industrial

CY7C1339G-200BGI
51-85115 119-ball Grid Array 14 x 22 x mm

CY7C1339G-200BGXI
288909 See ECN VBL In Ordering Info section, Changed TQFP to PB-free TQFP

Added PB-free BG package
332895 See ECN SYT Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA

Package as per JEDEC standards and updated the Pin Definitions accordingly

Modified VOL, VOH test conditions Replaced TBDs for ΘJA and ΘJC to their respective values on the Thermal Resistance table
Updated the Ordering Information by shading and unshading MPNs as per
availability
351194 See ECN PCI Updated Ordering Information Table
366728 See ECN PCI Added VDD/VDDQ test conditions in DC Table

Modified test condition in note# 10 from VIH < VDD to VIH < VDD
420883 See ECN RXU Converted from Preliminary to Final

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court”

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering Information table

Replaced Package Diagram of 51-85050 from *A to *B

Added Automotive Range in Operating Range Table
Updated the Ordering Information
480368 See ECN VKN Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Updated the Ordering Information table.

Page 18 of 18 [+] Feedback

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Datasheet ID: CY7C1339G-133AXET 507971