CY7C1338G-117AXC

CY7C1338G-117AXC Datasheet

CY7C1338G

Part	Datasheet
CY7C1338G-117AXC	CY7C1338G-117AXC (pdf)

PDF Datasheet Preview
CY7C1338G 4-Mbit 128K x 32 Flow-Through Sync SRAM • 128K X 32 common I/O • 3.3V and +10% core power supply VDD • 2.5V or 3.3V I/O supply VDDQ • Fast clock-to-output times ns 133-MHz version ns 117-MHz version ns 100-MHz version • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Lead-Free 100-pin TQFP and 119-ball BGA packages • “ZZ” Sleep Mode option Logic Block Diagram A0, A1, A MODE ADV CLK ADDRESS REGISTER A[1:0] BURST Q1 COUNTER AND LOGIC ADSC ADSP DQD BYTE WRITE REGISTER DQC BYTE WRITE REGISTER DQB BYTE WRITE REGISTER BWA BWE GW CE1 CE2 CE3 OE DQA BYTE WRITE REGISTER ENABLE REGISTER SLEEP CONTROL Functional Description[1] The CY7C1338G is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 133-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CCoEn1tr o, ldeinppthu-tesxp AanDsSioCn, Chip Enables ADSP, and CE2 and CE3 , Burst ADV , Write Enables BW[A:D], and inputs include BWE , and Global the Output Enable Write GW . OE and the Asynchronous ZZ pin. The CY7C1338G allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by Ordering Information Speed MHz Ordering Code Package Name Package Type Operating Range 133 CY7C1338G-133AXC A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial CY7C1338G-133BGC BG119 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-133BGXC BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-133AXI A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial CY7C1338G-133BGI BG119 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-133BGXI BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm 117 CY7C1338G-117AXC A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial CY7C1338G-117BGC BG119 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-117BGXC BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-117AXI A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial CY7C1338G-117BGI BG119 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-117BGXI BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm 100 CY7C1338G-100AXC A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial CY7C1338G-100BGC BG119 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-100BGXC BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-100AXI A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial CY7C1338G-100BGI BG119 119-Ball PBGA 14 x 22 x 2.4mm CY7C1338G-100BGXI BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BGX package will be available in Notes Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. DQs are in high-Z when exiting ZZ sleep mode. Page 14 of 17 Package Diagrams 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 100 1 81 80 Changed TQFP to PB-Free TQFP in Ordering Info section Added PB-Free BG package Page 17 of 17

PDF Datasheet Preview

CY7C1338G
4-Mbit 128K x 32 Flow-Through Sync SRAM
• 128K X 32 common I/O
• 3.3V and +10% core power supply VDD
• 2.5V or 3.3V I/O supply VDDQ
• Fast clock-to-output times
ns 133-MHz version ns 117-MHz version ns 100-MHz version
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Lead-Free 100-pin TQFP and 119-ball BGA packages
• “ZZ” Sleep Mode option

Logic Block Diagram

A0, A1, A

MODE ADV CLK

ADDRESS REGISTER

A[1:0]

BURST Q1

COUNTER

AND LOGIC

ADSC ADSP

DQD BYTE WRITE REGISTER

DQC BYTE WRITE REGISTER

DQB BYTE WRITE REGISTER

BWA BWE

GW CE1 CE2 CE3 OE

DQA BYTE WRITE REGISTER

ENABLE REGISTER

SLEEP CONTROL

Functional Description[1]

The CY7C1338G is a 131,072 x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
ns 133-MHz version . A 2-bit on-chip counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-triggered

Clock Input CLK . The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable

CCoEn1tr o, ldeinppthu-tesxp AanDsSioCn,

Chip Enables ADSP, and

CE2 and CE3 , Burst ADV , Write Enables

BW[A:D], and inputs include

BWE , and Global the Output Enable

Write GW . OE and the

Asynchronous ZZ pin.

The CY7C1338G allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input.

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by
Ordering Information

Speed MHz
Ordering Code

Package Name

Package Type

Operating Range
133 CY7C1338G-133AXC

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial

CY7C1338G-133BGC

BG119 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-133BGXC BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-133AXI

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial

CY7C1338G-133BGI

BG119 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-133BGXI BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm
117 CY7C1338G-117AXC

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial

CY7C1338G-117BGC

BG119 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-117BGXC BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-117AXI

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial

CY7C1338G-117BGI

BG119 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-117BGXI BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm
100 CY7C1338G-100AXC

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Commercial

CY7C1338G-100BGC

BG119 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-100BGXC BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-100AXI

A101 Lead-Free 100-Lead Thin Quad Flat Pack 14 x 20 x 1.4mm Industrial

CY7C1338G-100BGI

BG119 119-Ball PBGA 14 x 22 x 2.4mm

CY7C1338G-100BGXI BG119 Lead-Free 119-Ball PBGA 14 x 22 x 2.4mm

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BGX package will be available in

Notes Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. DQs are in high-Z when exiting ZZ sleep mode.

Page 14 of 17

Package Diagrams
100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101
100 1
81 80
Changed TQFP to PB-Free TQFP in Ordering Info section

Added PB-Free BG package

Page 17 of 17

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Datasheet ID: CY7C1338G-117AXC 507970