CY7C1338B-100AC

CY7C1338B-100AC Datasheet

CY7C1338B

Part	Datasheet
CY7C1338B-100AC	CY7C1338B-100AC (pdf)

PDF Datasheet Preview
338B CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 32 common I/O • Fast clock-to-output times ns 117-MHz version • Two-bit wraparound counter supporting either interleaved or linear burst sequence • Separate processor and controller address strobes provide direct interface with the processor and external cache controller • Synchronous self-timed write • Asynchronous output enable • 3.3V/ 2.5V I/Os • JEDEC-standard pinout • 100-pin TQFP packaging • ZZ “sleep” mode • Available in Commercial and Industrial Temperatures The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 117-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. The CY7C1338B allows both interleaved and linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control. Logic Block Diagram CLK ADV ADSC ADSP A[16:0] 17 BWE BW 3 BW 0 CE1 CE2 CE 3 MODE A0,A1 2 BURST Q0 CE COUNTER Q ADDRESS REGISTER D DQ[31:24] Q BYTEWRITE REGISTERS D DQ[23:16] Q BYTEWRITE REGISTERS D DQ[15:8] Q BYTEWRITE REGISTERS D DQ[7:0] Q BYTEWRITE REGISTERS ENABLE REGISTER 128K X 32 MEMORY ARRAY SLEEP CONTROL INPUT REGISTERS CLK DQ[31:0] Selection Guide Maximum Access Time ns Maximum Operating Current mA Maximum Standby Current mA Pentium is a registered trademark of Intel Corporation. -117 -100 Ordering Information Speed MHz Ordering Code CY7C1338B-117AC CY7C1338B-117BGC CY7C1338B-100AC CY7C1338B-100BGC CY7C1338B-100AI CY7C1338B-100BGI Package Name A101 BG119 A101 BG119 A101 BG119 Package Type 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA Package Diagrams 100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101 CY7C1338B Operating Range Commercial Industrial 51-85050-A Page 16 of 18 Package Diagrams continued 119-Lead FBGA 14 x 22 x mm BG119 CY7C1338B 51-85115 Page 17 of 18 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1338B Document Title CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Document Number 38-05143 ECN NO. Issue Date Orig. of Change Description of Change 109887 09/15/01 Change from Spec number 38-00939 to 38-05143 Page 18 of 18

PDF Datasheet Preview

338B

CY7C1338B
128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description
• Supports 117-MHz microprocessor cache systems with zero wait states
• 128K by 32 common I/O
• Fast clock-to-output times
ns 117-MHz version
• Two-bit wraparound counter supporting either interleaved or linear burst sequence
• Separate processor and controller address strobes provide direct interface with the processor and external cache controller
• Synchronous self-timed write
• Asynchronous output enable
• 3.3V/ 2.5V I/Os
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
• Available in Commercial and Industrial Temperatures

The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is ns 117-MHz version . A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

The CY7C1338B allows both interleaved and linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs. Address advancement is controlled by the Address Advancement ADV input.

A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control.

Logic Block Diagram

CLK ADV ADSC ADSP

A[16:0] 17

BWE BW 3

BW 0 CE1 CE2 CE 3

MODE

A0,A1 2

BURST Q0

CE COUNTER

Q ADDRESS

REGISTER

D DQ[31:24] Q BYTEWRITE REGISTERS

D DQ[23:16] Q BYTEWRITE REGISTERS

D DQ[15:8] Q BYTEWRITE REGISTERS

D DQ[7:0] Q BYTEWRITE REGISTERS

ENABLE REGISTER
128K X 32

MEMORY

ARRAY

SLEEP

CONTROL

INPUT REGISTERS CLK

DQ[31:0]

Selection Guide

Maximum Access Time ns Maximum Operating Current mA Maximum Standby Current mA

Pentium is a registered trademark of Intel Corporation.
-117
-100
Ordering Information

Speed MHz
Ordering Code CY7C1338B-117AC CY7C1338B-117BGC CY7C1338B-100AC CY7C1338B-100BGC CY7C1338B-100AI CY7C1338B-100BGI

Package Name A101 BG119 A101 BG119 A101 BG119

Package Type 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA

Package Diagrams
100-Pin Thin Plastic Quad Flatpack 14 x 20 x mm A101

CY7C1338B

Operating Range

Commercial

Industrial
51-85050-A

Page 16 of 18

Package Diagrams continued
119-Lead FBGA 14 x 22 x mm BG119

CY7C1338B
51-85115

Page 17 of 18

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1338B

Document Title CY7C1338B 128K x 32 Synchronous-Flow-Through 3.3V Cache RAM Document Number 38-05143

ECN NO.

Issue Date

Orig. of Change

Description of Change
109887 09/15/01

Change from Spec number 38-00939 to 38-05143

Page 18 of 18

More datasheets: CY7C1399B-15ZXC | 76002021 | ECM-9 | ECM-8 | ECM-2 | ECM-7 | ECM-6 | ECM-3 | W4E300-CP30-70 | W4E300-CP26-70

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1338B-100AC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1338B-100AC 507969