CY7C1329H-166AXC

CY7C1329H-166AXC Datasheet

CY7C1329H

Part	Datasheet
CY7C1329H-166AXC	CY7C1329H-166AXC (pdf)

Related Parts	Information
CY7C1329H-166AXCT	CY7C1329H-166AXCT

PDF Datasheet Preview
CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM • Registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times ns for 166-MHz device ns for 133-MHz device • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Offered in JEDEC-standard lead-free 100-pin TQFP package • “ZZ” Sleep Mode Option Logic Block Diagram Functional Description[1] The CY7C1329H SRAM integrates 64K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BW[A:D] and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV . Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1329H operates from a +3.3V core power supply while all outputs operate with either a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. A0, A1, A MODE ADV CLK ADSC ADSP BWA BWE GW CE1 CE2 CE3 OE ADDRESS REGISTER A[1:0] BURST COUNTER CLR AND Q0 LOGIC DQD BYTE WRITE REGISTER DQC BYTE WRITE REGISTER DQB BYTE WRITE REGISTER DQA BYTE WRITE REGISTER ENABLE REGISTER PIPELINED ENABLE DQD BYTE WRITE DRIVER DQC BYTE WRITE DRIVER DQB BYTE WRITE DRIVER DQA BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS INPUT REGISTERS SLEEP CONTROL Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code CY7C1329H-166AXC CY7C1329H-133AXC Package Diagram Package Diagram 51-85050 51-85050 Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free Operating Range Commercial Commercial 100-pin TQFP 14 x 20 x mm 51-85050 51-85050-C i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders. Page 15 of 16 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1329H Document History Page Document Title CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Document Number 38-05673 Orig. of ECN NO. Issue Date Change Description of Change 347357 See ECN PCI New Data Sheet 424820 See ECN RXU Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed Three-State to Tri-State. Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Modified test condition from VIH < VDD to VIH < VDD Replaced Package Name column with Package Diagram in the Ordering Information table. Updated the Ordering Information Table. Replaced Package Diagram of 51-85050 from A to *B 433014 See ECN NXR Included 3.3V I/O option Updated the Ordering Information table. 2896585 03/20/2010 NJY Removed obsolete part numbers from Ordering Information table and updated package diagrams. Page 16 of 16 [+] Feedback

PDF Datasheet Preview

CY7C1329H
2-Mbit 64K x 32 Pipelined Sync SRAM
• Registered inputs and outputs for pipelined operation
• 64K x 32 common I/O architecture
• 3.3V core power supply
• 2.5V/3.3V I/O operation
• Fast clock-to-output times
ns for 166-MHz device ns for 133-MHz device
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in JEDEC-standard lead-free 100-pin TQFP package
• “ZZ” Sleep Mode Option

Logic Block Diagram

Functional Description[1]

The CY7C1329H SRAM integrates 64K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable CE1 , depth-expansion Chip Enables CE2 and CE3 , Burst Control inputs ADSC, ADSP, and ADV , Write Enables BW[A:D] and BWE , and Global Write GW . Asynchronous inputs include the Output Enable OE and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV .

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. This part supports Byte Write operations see Pin Descriptions and Truth Table for further details . Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written.

The CY7C1329H operates from a +3.3V core power supply while all outputs operate with either a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

A0, A1, A

MODE ADV CLK

ADSC ADSP

BWA BWE

GW CE1 CE2 CE3 OE

ADDRESS REGISTER

A[1:0]

BURST COUNTER CLR AND Q0

LOGIC

DQD BYTE WRITE REGISTER

DQC BYTE WRITE REGISTER

DQB BYTE WRITE REGISTER

DQA BYTE WRITE REGISTER

ENABLE REGISTER

PIPELINED ENABLE

DQD BYTE WRITE DRIVER

DQC BYTE WRITE DRIVER

DQB BYTE WRITE DRIVER

DQA BYTE WRITE DRIVER

MEMORY ARRAY

SENSE AMPS

OUTPUT REGISTERS

OUTPUT BUFFERS

INPUT REGISTERS

SLEEP

CONTROL

Note For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Selection Guide

Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code CY7C1329H-166AXC CY7C1329H-133AXC

Package Diagram

Package Diagram
51-85050
51-85050

Package Type 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free 100-pin Thin Quad Flat Pack 14 x 20 x mm Lead-Free

Operating Range

Commercial

Commercial
100-pin TQFP 14 x 20 x mm 51-85050
51-85050-*C
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.

Page 15 of 16

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY7C1329H

Document History Page

Document Title CY7C1329H 2-Mbit 64K x 32 Pipelined Sync SRAM Document Number 38-05673

Orig. of ECN NO. Issue Date Change

Description of Change
347357 See ECN

PCI New Data Sheet
424820 See ECN RXU Converted from Preliminary to Final.

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Changed Three-State to Tri-State.

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table.
Modified test condition from VIH < VDD to VIH < VDD Replaced Package Name column with Package Diagram in the Ordering

Information table.
Updated the Ordering Information Table.

Replaced Package Diagram of 51-85050 from *A to *B
433014 See ECN NXR Included 3.3V I/O option
Updated the Ordering Information table.
2896585 03/20/2010 NJY Removed obsolete part numbers from Ordering Information table and
updated package diagrams.

Page 16 of 16 [+] Feedback

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Datasheet ID: CY7C1329H-166AXC 507967