CY7C1329-100AC

CY7C1329-100AC Datasheet

CY7C1329

Part	Datasheet
CY7C1329-100AC	CY7C1329-100AC (pdf)

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CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM • Supports 133-MHz bus for and PowerPC operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 64K x 32 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times ns for 133-MHz device ns for 100-MHz device • User-selectable burst counter supporting Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • JEDEC-standard 100-lead TQFP pinout • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through Logic Block Diagram CLK ADV ADSC ADSP A[15:0] 16 BWE BW 3 MODE A[1:0] 2 BURST Q0 CE COUNTER ADDRESS REGISTER D DQ[31:24] Q BYTEWRITE REGISTERS D DQ[23:16] Q BYTEWRITE REGISTERS D DQ[15:8] Q BYTEWRITE REGISTERS CE1 CE2 CE3 D DQ[7:0] Q BYTEWRITE REGISTERS ENABLE REGISTER output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is ns 133-MHz device . The CY7C1329 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the four Byte Write Select BW[3:0] inputs. A Global Write Enable GW overrides all Byte Write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a Read cycle when emerging from a deselected state. 64K x 32 Memory Array ENABLE DELAY REGISTER OUTPUT REGISTERS CLK INPUT REGISTERS SLEEP CONTROL Ordering Information Speed MHz Ordering Code CY7C1329-133AC CY7C1329-100AC Package Diagram Package Name A101 A101 Package Type 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack 100-lead Thin Plastic Quad Flatpack 14 x 20 x mm A101 CY7C1329 Operating Range Commercial 51-85050-A i486 is a trademark of Intel Corporation. Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Page 14 of 15 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Document Title CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Document Number:38-05279 ECN NO Issue Date Orig. of Change Description of changes 114388 03/25/02 DSG Change from Spec number 38-00561 to 38-05279 114499 04/11/02 GLC Changed to set-up CY7C1329 Page 15 of 15

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CY7C1329
64K x 32 Synchronous-Pipelined Cache RAM
• Supports 133-MHz bus for and PowerPC operations with zero wait states
• Fully registered inputs and outputs for pipelined operation
• 64K x 32 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
ns for 133-MHz device
ns for 100-MHz device
• User-selectable burst counter supporting

Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100-lead TQFP pinout
• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through

Logic Block Diagram

CLK ADV ADSC ADSP

A[15:0] 16

BWE BW 3

MODE

A[1:0] 2

BURST Q0

CE COUNTER

ADDRESS

REGISTER

D DQ[31:24] Q BYTEWRITE REGISTERS

D DQ[23:16] Q BYTEWRITE REGISTERS

D DQ[15:8] Q

BYTEWRITE REGISTERS

CE1 CE2 CE3

D DQ[7:0] Q BYTEWRITE REGISTERS

ENABLE REGISTER
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is ns 133-MHz device .

The CY7C1329 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte Write operations are qualified with the four Byte Write Select BW[3:0] inputs. A Global Write Enable GW overrides all Byte Write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed Write circuitry.

Three synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable OE provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a Read cycle when emerging from a deselected state.
64K x 32

Memory

Array

ENABLE DELAY

REGISTER

OUTPUT REGISTERS CLK

INPUT REGISTERS

SLEEP

CONTROL
Ordering Information

Speed MHz
Ordering Code CY7C1329-133AC CY7C1329-100AC

Package Diagram

Package Name

A101

A101

Package Type 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack
100-lead Thin Plastic Quad Flatpack 14 x 20 x mm A101

CY7C1329

Operating Range

Commercial
51-85050-A
i486 is a trademark of Intel Corporation. Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 14 of 15

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Document Title CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Document Number:38-05279

ECN NO

Issue Date

Orig. of Change

Description of changes
114388 03/25/02 DSG Change from Spec number 38-00561 to 38-05279
114499 04/11/02

GLC Changed to set-up

CY7C1329

Page 15 of 15

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Datasheet ID: CY7C1329-100AC 507965