CY7C1318CV18-250BZI

CY7C1318CV18-250BZI Datasheet


CY7C1318CV18, CY7C1320CV18

Part Datasheet
CY7C1318CV18-250BZI CY7C1318CV18-250BZI CY7C1318CV18-250BZI (pdf)
Related Parts Information
CY7C1320CV18-267BZXC CY7C1320CV18-267BZXC CY7C1320CV18-267BZXC
CY7C1320CV18-250BZC CY7C1320CV18-250BZC CY7C1320CV18-250BZC
CY7C1320CV18-167BZC CY7C1320CV18-167BZC CY7C1320CV18-167BZC
CY7C1318CV18-250BZXC CY7C1318CV18-250BZXC CY7C1318CV18-250BZXC
CY7C1318CV18-250BZC CY7C1318CV18-250BZC CY7C1318CV18-250BZC
CY7C1318CV18-167BZC CY7C1318CV18-167BZC CY7C1318CV18-167BZC
CY7C1318CV18-200BZXC CY7C1318CV18-200BZXC CY7C1318CV18-200BZXC
CY7C1318CV18-200BZI CY7C1318CV18-200BZI CY7C1318CV18-200BZI
CY7C1320CV18-250BZXC CY7C1320CV18-250BZXC CY7C1320CV18-250BZXC
PDF Datasheet Preview
CY7C1318CV18, CY7C1320CV18
18-Mbit DDR II SRAM 2-Word Burst Architecture
18-Mbit DDR II SRAM 2-Word Burst Architecture
• 18-Mbit density 1 M x 18, 512 K x 36
• 267-MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate DDR interfaces
data transferred at 534 MHz at 267 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock
skew and flight time mismatches
• Echo clocks CQ and CQ simplify data capture in high speed
systems
• Synchronous internally self-timed writes
• DDR II operates with cycle read latency when delay lock
loop DLL is enabled
• Operates similar to a DDR I device with one cycle read latency
in DLL Off mode
• V core power supply with high-speed transceiver logic

HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage V VDD
• Available in 165-ball fine pitch ball grid array FPBGA package
13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• DLL for accurate data placement

Configurations

CY7C1318CV18 1M x 18 CY7C1320CV18 512K x 36

Functional Description

The CY7C1318CV18, and CY7C1320CV18 are V synchronous pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a one-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. For CY7C1318CV18 and CY7C1320CV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1318CV18 of two 36-bit words in the case of CY7C1320CV18 sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs, D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need to capture data separately from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
• San Jose, CA 95134-1709
• 408-943-2600
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Logic Block Diagram CY7C1318CV18

CY7C1318CV18, CY7C1320CV18

Burst

Logic

A 19:0
20 19 A 19:1

Address Register

K DOFF

CLK Gen.

VREF R/W BWS[1:0]

Control Logic

Write Add. Decode Read Add. Decode

Write Reg

Write Reg
512K x 18 Array 512K x 18 Array

Read Data Reg. 36 18

Output Logic

Control

Reg.

Reg. 18

Reg.

DQ[17:0]

Logic Block Diagram CY7C1320CV18
Power Up Sequence 19 DLL Constraints 19 Maximum Ratings 20 Operating Range 20 Neutron Soft Error Immunity 20 Electrical Characteristics 20 DC Electrical Characteristics 20 AC Electrical Characteristics 21 Capacitance 21 Thermal Resistance 21 Switching Characteristics 22 Switching Waveforms 24 Ordering Information 25 Ordering Code Definition 25 Package Diagram 26 Acronyms 27 Document Conventions 27 Units of Measure 27 Document History Page 28 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 PSoC Solutions 29

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Selection Guide

Description Maximum operating frequency Maximum operating current

CY7C1318CV18, CY7C1320CV18
267 MHz
250 MHz 250 730 775
200 MHz 200 600 635
167 MHz 167 510 540

Unit MHz mA

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CY7C1318CV18, CY7C1320CV18

Pin Configuration

The pin configuration for CY7C1318CV18 and CY7C1320CV18 follow.[1]
165-ball FBGA 13 x 15 x mm Pinout

CY7C1318CV18 1M x 18

CQ NC/72M

BWS1

K NC/144M LD

A NC/288M K

BWS0

DQ10

DQ11

VDDQ

VDDQ

DQ12

VDDQ

VDDQ

DQ13

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DQ14

VDDQ

VDDQ
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
267 CY7C1320CV18-267BZXC
250 CY7C1318CV18-250BZC

CY7C1320CV18-250BZC

CY7C1318CV18-250BZXC

CY7C1320CV18-250BZXC

CY7C1318CV18-250BZI
200 CY7C1318CV18-200BZXC

CY7C1318CV18-200BZI
167 CY7C1318CV18-167BZC

CY7C1320CV18-167BZC

Package Diagram

Package Type
51-85180 165-ball FBGA 13 x 15 x mm Pb-free
51-85180 165-ball FBGA 13 x 15 x mm
51-85180 165-ball FBGA 13 x 15 x mm Pb-free
51-85180 165-ball FBGA 13 x 15 x mm 51-85180 165-ball FBGA 13 x 15 x mm Pb-free 51-85180 165-ball FBGA 13 x 15 x mm 51-85180 165-ball FBGA 13 x 15 x mm
Ordering Code Definition

CY 7 C
13XX

C V18 - XXX BZ X, C, I

Package Type BZ = FBGA, X = Pb-free, C = Commercial, I = Industrial

Operating Range

Commercial

Industrial Commercial

Industrial Commercial

Maximum operating frequency

Voltage V

Technology CMOS Marketing Code 7 = SRAM

Company ID CY = Cypress

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CY7C1318CV18, CY7C1320CV18

Package Diagram

Figure 165-ball FBGA 13 x 15 x mm , 51-85180
51-85180 *C

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Acronyms

Acronym DDR DLL FPBGA HSTL JEDEC JTAG SRAM SEL TDO TCK TDI TMS TAP

Description double data rate delay lock loop fine-pitch ball grid array high-speed transceiver logic Joint Electron Device Engineering Council joint test action group static random access memory single event latch up test data out test clock test data in test mode select test access port

Document Conventions

Units of Measure

Symbol ns V µA mA mm ms MHz pF W °C

Unit of Measure nano seconds Volts micro Amperes milli Amperes milli meter milli seconds Mega Hertz pico Farad Watts kilo ohms degree Celcius

CY7C1318CV18, CY7C1320CV18

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CY7C1318CV18, CY7C1320CV18

Document History Page

Document Title CY7C1318CV18/CY7C1320CV18, 18-Mbit DDR II SRAM 2-Word Burst Architecture Document Number 001-07160

ECN No.

Submission Date

Orig. of Change

Description of Change
** 433284 See ECN

New data sheet
*A 462615 See ECN

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform
*B 503690 See ECN

Minor change Moved data sheet to web
*F 2755838 08/25/2009 VKN/AESA Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information.
*G 2896382 04/09/2010
Removed obsolete part numbers from Ordering Information. Updated package
diagram, Sales, Solutions, and Legal Information section, and data sheet template.

Removed pruned part CY7C1320CV18-200BZC.
*H 2957481 06/21/2010
Included “CY7C1318CV18-250BZI” in Ordering Information Added Ordering Code Definition
*I 3096143 11/27/2010

Added Units of Measure.

Minor edits.

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CY7C1318CV18, CY7C1320CV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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More datasheets: SER0037 | CY7C1320CV18-267BZXC | CY7C1320CV18-250BZC | CY7C1320CV18-167BZC | CY7C1318CV18-250BZXC | CY7C1318CV18-250BZC | CY7C1318CV18-167BZC | CY7C1318CV18-200BZXC | CY7C1318CV18-200BZI | CY7C1320CV18-250BZXC


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Datasheet ID: CY7C1318CV18-250BZI 507960