CY7C1312CV18-250BZI

CY7C1312CV18-250BZI Datasheet


CY7C1312CV18 CY7C1314CV18

Part Datasheet
CY7C1312CV18-250BZI CY7C1312CV18-250BZI CY7C1312CV18-250BZI (pdf)
Related Parts Information
CY7C1312CV18-250BZC CY7C1312CV18-250BZC CY7C1312CV18-250BZC
CY7C1312CV18-200BZC CY7C1312CV18-200BZC CY7C1312CV18-200BZC
CY7C1312CV18-167BZI CY7C1312CV18-167BZI CY7C1312CV18-167BZI
CY7C1312CV18-167BZC CY7C1312CV18-167BZC CY7C1312CV18-167BZC
CY7C1312CV18-250BZXC CY7C1312CV18-250BZXC CY7C1312CV18-250BZXC
CY7C1314CV18-250BZC CY7C1314CV18-250BZC CY7C1314CV18-250BZC
CY7C1314CV18-200BZC CY7C1314CV18-200BZC CY7C1314CV18-200BZC
CY7C1314CV18-167BZC CY7C1314CV18-167BZC CY7C1314CV18-167BZC
CY7C1314CV18-200BZI CY7C1314CV18-200BZI CY7C1314CV18-200BZI
PDF Datasheet Preview
CY7C1312CV18 CY7C1314CV18
18-Mbit II SRAM 2-Word Burst Architecture
• Separate independent Read and Write Data Ports Supports concurrent transactions
• 250 MHz Clock for High Bandwidth
• 2-word Burst on all Accesses
• Double Data Rate DDR Interfaces on both Read and Write Ports data transferred at 500 MHz at 250 MHz
• Two Input Clocks K and K for precise DDR Timing SRAM uses rising edges only
• Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches
• Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems
• Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports
• Separate Port Selects for Depth Expansion
• Synchronous internally Self-timed Writes
• II operates with Cycle Read Latency when Delay

Lock Loop DLL is enabled
• Operates similar to a QDR I Device with one Cycle Read Latency in DLL Off Mode
• Available in x18, and x36 Configurations
• Full Data Coherency, providing Most Current Data
• Core VDD = 1.8V ±0.1V IO VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA Package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free Packages
• Variable Drive HSTL Output Buffers
• JTAG compatible Test Access Port
• Delay Lock Loop DLL for accurate Data Placement

Selection Guide

Maximum Operating Frequency

Maximum Operating Current
250 MHz 250 800 900

Configurations

CY7C1312CV18 1M x 18

CY7C1314CV18 512K x 36

Functional Description

The CY7C1312CV18, and CY7C1314CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 18-bit words CY7C1312CV18 , or 36-bit words CY7C1314CV18 that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
200 MHz 200 675 750
167 MHz 167 600 650

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
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Logic Block Diagram CY7C1312CV18

CY7C1312CV18 CY7C1314CV18

D[17:0]

A 18:0 19
Power Up Sequence 18 DLL Constraints 18 Maximum Ratings 19 Operating Range 19 Neutron Soft Error Immunity 19 Electrical Characteristics 19 DC Electrical Characteristics 19 AC Electrical Characteristics 20 Capacitance 20 Thermal Resistance 20 Switching Characteristics 21 Switching Waveforms 22 Ordering Information 23 Package Diagram 24 Sales, Solutions, and Legal Information 25 Worldwide Sales and Design Support 25 Document History Page 25 Products 25

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CY7C1312CV18 CY7C1314CV18

Pin Configuration

The pin configuration for CY7C1312CV18 and CY7C1314CV18 follow.[1]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C1312CV18 1M x 18

CQ NC/144M NC/36M WPS BWS1

K NC/288M RPS

BWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

NC/72M CQ

VDDQ

VREF

CY7C1314CV18 512K x 36

CQ NC/288M NC/72M WPS BWS2

BWS1 RPS NC/36M NC/144M CQ

BWS3

BWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
250 CY7C1312CV18-250BZC

CY7C1314CV18-250BZC

CY7C1312CV18-250BZXC

CY7C1312CV18-250BZI
200 CY7C1312CV18-200BZC

CY7C1314CV18-200BZC

CY7C1314CV18-200BZI 167 CY7C1312CV18-167BZC

CY7C1314CV18-167BZC CY7C1312CV18-167BZI

Package Diagram

Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Operating Range

Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

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CY7C1312CV18 CY7C1314CV18

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW PIN 1 CORNER

M C M C A B 165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180 *C

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CY7C1312CV18 CY7C1314CV18

Document History Page
*F 2755838 08/25/2009 VKN/AESA Removed x8 and x9 part number details Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information.
*G 2822813 12/07/09 VKN/PYRS Included CY7C1312CV18-250BZI part in Ordering Information table.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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More datasheets: FIT0096 | CY7C1312CV18-250BZC | CY7C1312CV18-200BZC | CY7C1312CV18-167BZI | CY7C1312CV18-167BZC | CY7C1312CV18-250BZXC | CY7C1314CV18-250BZC | CY7C1314CV18-200BZC | CY7C1314CV18-167BZC | CY7C1314CV18-200BZI


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Datasheet ID: CY7C1312CV18-250BZI 507954