CY7C1911JV18-300BZC

CY7C1911JV18-300BZC Datasheet

CY7C1311JV18/CY7C1911JV18

Part	Datasheet
CY7C1911JV18-300BZC	CY7C1911JV18-300BZC (pdf)

Related Parts	Information
CY7C1315JV18-300BZC	CY7C1315JV18-300BZC
CY7C1315JV18-300BZXC	CY7C1315JV18-300BZXC

PDF Datasheet Preview
CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 18-Mbit II SRAM 4-Word Burst Architecture • Separate Independent Read and Write Data Ports Supports concurrent transactions • 300 MHz Clock for High Bandwidth • 4-word Burst for reducing Address Bus Frequency • Double Data Rate DDR interfaces on both read and write ports data transferred at 600 MHz at 300 MHz • Two Input Clocks K and K for Precise DDR Timing SRAM uses rising edges only • Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches • Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems • Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports • Separate Port Selects for Depth Expansion • Synchronous Internally Self-timed Writes • II Operates with Cycle Read Latency when the Delay Lock Loop DLL is enabled • Operates like a QDR I device with 1 Cycle Read Latency in DLL Off Mode • Available in x8, x9, x18, and x36 configurations • Full Data Coherency, providing most current Data • Core VDD = ±0.1V IO VDDQ = 1.4V to VDD • Available in 165-Ball FBGA Package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • Variable Drive HSTL Output Buffers • JTAG Compatible Test Access Port • Delay Lock Loop DLL for Accurate Data Placement Configurations CY7C1311JV18 2M x 8 CY7C1911JV18 2M x 9 CY7C1313JV18 1M x 18 CY7C1315JV18 512K x 36 Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II read and write ports are completely independent of one another. In order to maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with four 8-bit words CY7C1311JV18 or 9-bit words CY7C1911JV18 or 18-bit words CY7C1313JV18 or 36-bit words CY7C1315JV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus ‘turnarounds’. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 300 MHz 250 MHz 250 665 675 705 830 Unit MHz mA • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1311JV18 CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18 D[7:0] Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 300 CY7C1311JV18-300BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1911JV18-300BZC CY7C1313JV18-300BZC CY7C1315JV18-300BZC CY7C1311JV18-300BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1911JV18-300BZXC CY7C1313JV18-300BZXC CY7C1315JV18-300BZXC CY7C1311JV18-300BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1911JV18-300BZI CY7C1313JV18-300BZI CY7C1315JV18-300BZI CY7C1311JV18-300BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1911JV18-300BZXI CY7C1313JV18-300BZXI CY7C1315JV18-300BZXI 250 CY7C1311JV18-250BZC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1911JV18-250BZC CY7C1313JV18-250BZC CY7C1315JV18-250BZC CY7C1311JV18-250BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free CY7C1911JV18-250BZXC CY7C1313JV18-250BZXC CY7C1315JV18-250BZXC CY7C1311JV18-250BZI 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1911JV18-250BZI

PDF Datasheet Preview

CY7C1311JV18/CY7C1911JV18

CY7C1313JV18/CY7C1315JV18
18-Mbit II SRAM 4-Word Burst Architecture
• Separate Independent Read and Write Data Ports Supports concurrent transactions
• 300 MHz Clock for High Bandwidth
• 4-word Burst for reducing Address Bus Frequency
• Double Data Rate DDR interfaces on both read and write ports data transferred at 600 MHz at 300 MHz
• Two Input Clocks K and K for Precise DDR Timing SRAM uses rising edges only
• Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches
• Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems
• Single Multiplexed Address Input Bus latches Address Inputs for both Read and Write Ports
• Separate Port Selects for Depth Expansion
• Synchronous Internally Self-timed Writes
• II Operates with Cycle Read Latency when the Delay

Lock Loop DLL is enabled
• Operates like a QDR I device with 1 Cycle Read Latency in DLL Off Mode
• Available in x8, x9, x18, and x36 configurations
• Full Data Coherency, providing most current Data
• Core VDD = ±0.1V IO VDDQ = 1.4V to VDD
• Available in 165-Ball FBGA Package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• Variable Drive HSTL Output Buffers
• JTAG Compatible Test Access Port
• Delay Lock Loop DLL for Accurate Data Placement

Configurations

CY7C1311JV18 2M x 8

CY7C1911JV18 2M x 9

CY7C1313JV18 1M x 18

CY7C1315JV18 512K x 36

Functional Description

The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II read and write ports are completely independent of one another. In order to maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with four 8-bit words CY7C1311JV18 or 9-bit words CY7C1911JV18 or 18-bit words CY7C1313JV18 or 36-bit words CY7C1315JV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus ‘turnarounds’.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description Maximum Operating Frequency Maximum Operating Current
300 MHz
250 MHz 250 665 675 705 830

Unit MHz mA
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1311JV18

CY7C1311JV18/CY7C1911JV18 CY7C1313JV18/CY7C1315JV18

D[7:0]
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
300 CY7C1311JV18-300BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1911JV18-300BZC

CY7C1313JV18-300BZC

CY7C1315JV18-300BZC

CY7C1311JV18-300BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1911JV18-300BZXC

CY7C1313JV18-300BZXC

CY7C1315JV18-300BZXC

CY7C1311JV18-300BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1911JV18-300BZI

CY7C1313JV18-300BZI

CY7C1315JV18-300BZI

CY7C1311JV18-300BZXI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1911JV18-300BZXI

CY7C1313JV18-300BZXI

CY7C1315JV18-300BZXI
250 CY7C1311JV18-250BZC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1911JV18-250BZC

CY7C1313JV18-250BZC

CY7C1315JV18-250BZC

CY7C1311JV18-250BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

CY7C1911JV18-250BZXC

CY7C1313JV18-250BZXC

CY7C1315JV18-250BZXC

CY7C1311JV18-250BZI
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1911JV18-250BZI

More datasheets: 892607 RD013 | 892607 WH013 | 892607 SL013 | 892607 OR013 | 892607 GR013 | 892607 BR013 | 892607 BL013 | 892607 BK013 | 892607 YL013 | 892607 VI013

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1911JV18-300BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1911JV18-300BZC 507953