CY7C12451KV18-400BZC

CY7C12451KV18-400BZC Datasheet

CY7C12411KV18, CY7C12561KV18

Part	Datasheet
CY7C12451KV18-400BZC	CY7C12451KV18-400BZC (pdf)

Related Parts	Information
CY7C12451KV18-400BZXC	CY7C12451KV18-400BZXC

PDF Datasheet Preview
CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 36-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency • Separate Independent Read and Write Data Ports Supports concurrent transactions • 450 MHz Clock for High Bandwidth • 4-word Burst for Reducing Address Bus Frequency • Double Data Rate DDR Interfaces on both Read and Write Ports Data transferred at 900 MHz at 450 MHz • Available in Clock Cycle Latency • Two Input Clocks K and K for Precise DDR Timing SRAM uses rising edges only • Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems • Data Valid Pin QVLD to indicate Valid Data on the Output • Single Multiplexed Address Input Bus Latches Address Inputs for Read and Write Ports • Separate Port Selects for Depth Expansion • Synchronous Internally Self Timed Writes • II+ operates with Cycle Read Latency when DOFF is asserted HIGH • Operates similar to QDR-I Device with 1 Cycle Read Latency when DOFF is asserted LOW • Available in x8, x9, x18, and x36 Configurations • Full Data Coherency, providing most Current Data • Core VDD = 1.8V± 0.1V I/O VDDQ = 1.4V to VDD[1] Supports both 1.5V and 1.8V I/O supply • HSTL Inputs and Variable Drive HSTL Output Buffers • Available in 165-Ball FBGA Package 13 x 15 x mm • Offered in both Pb-free and non Pb-free Packages • JTAG Compatible Test Access Port • Phase Locked Loop PLL for Accurate Data Placement Configurations With Read Cycle Latency of cycles CY7C12411KV18 4M x 8 CY7C12561KV18 4M x 9 CY7C12431KV18 2M x 18 CY7C12451KV18 1M x 36 Functional Description The CY7C12411KV18, CY7C12561KV18, CY7C12431KV18, and CY7C12451KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words CY7C12411KV18 , 9-bit words CY7C12561KV18 , 18-bit words CY7C12431KV18 , or 36-bit words CY7C12451KV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus “turnarounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. These devices are down bonded from the 65nm 72M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and the same JTAG ID code as the equivalent 72M device options. For details refer to the application note AN53189, 65nm Technology InterimQDRII+/DDRII+ SRAM device family description. Table Selection Guide 450 MHz Max Operating Frequency 450 Max Operating Current x8 760 x9 760 x18 780 x36 1100 400 MHz 400 690 710 1000 375 MHz 375 660 680 950 333 MHz 333 600 620 850 Unit MHz mA Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD. TAP Registers 13 TAP Instruction Set 13 TAP Controller State 15 TAP Controller Block 16 TAP Electrical Characteristics 16 TAP AC Switching Characteristics 17 TAP Timing and Test Conditions 17 Identification Register Definitions 18 Scan Register Sizes 18 Instruction 18 Boundary Scan Order 19 Power Up Sequence in QDR II+ SRAM 20 Power Up Sequence 20 PLL 20 Maximum 21 Operating Range 21 Neutron Soft Error 21 Electrical Characteristics 21 DC Electrical 21 AC Electrical 22 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence 25 Ordering Information 26 Package Diagram 26 Document History 27 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support....................... 28 Products 28 PSoC Solutions 28 Page 4 of 28 [+] Feedback CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 Pin Configuration The pin configuration for CY7C12411KV18, CY7C12561KV18, CY7C12431KV18, and CY7C12451KV18 follow.[2] 165-Ball FBGA 13 x 15 x mm Pinout CY7C12411KV18 4M x 8 CQ NC/72M WPS NWS1 K NC/144M RPS A NC/288M K NWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ QVLD CY7C12561KV18 4M x 9 CQ NC/72M K NC/144M RPS A NC/288M K BWS0 VDDQ VDDQ VDDQ VDDQ Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code 400 CY7C12451KV18-400BZC CY7C12451KV18-400BZXC Package Diagram Package Type Operating Range 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180-C Page 26 of 28 [+] Feedback CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 Document History Page Document Title 36-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency Document Number 001-53192 Orig. Of Change Submission Date Description Of Change * 2702761 VKN/PYRS 05/06/2009 New data sheet A 2747635 VKN/AESA 08/03/2009 Converted from preliminary to final For 450 MHz speed, changed tCO, tCCQO, tCHZ from 370ps to 450ps and tDOH, tCQOH, tCLZ from -370ps to -450ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information B 2761928 09/10/2009 Post to external web. C 2767155 09/23/2009 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer D 2855911 01/18/2010 Included “CY7C12451KV18-400BZXC” part in the Ordering information table Updated package outline diagram Page 27 of 28 [+] Feedback CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 28 of 28 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C12411KV18, CY7C12561KV18

CY7C12431KV18, CY7C12451KV18
36-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency
• Separate Independent Read and Write Data Ports Supports concurrent transactions
• 450 MHz Clock for High Bandwidth
• 4-word Burst for Reducing Address Bus Frequency
• Double Data Rate DDR Interfaces on both Read and Write Ports Data transferred at 900 MHz at 450 MHz
• Available in Clock Cycle Latency
• Two Input Clocks K and K for Precise DDR Timing SRAM uses rising edges only
• Echo Clocks CQ and CQ simplify Data Capture in High Speed Systems
• Data Valid Pin QVLD to indicate Valid Data on the Output
• Single Multiplexed Address Input Bus Latches Address Inputs for Read and Write Ports
• Separate Port Selects for Depth Expansion
• Synchronous Internally Self Timed Writes
• II+ operates with Cycle Read Latency when DOFF
is asserted HIGH
• Operates similar to QDR-I Device with 1 Cycle Read Latency when DOFF is asserted LOW
• Available in x8, x9, x18, and x36 Configurations
• Full Data Coherency, providing most Current Data
• Core VDD = 1.8V± 0.1V I/O VDDQ = 1.4V to VDD[1]

Supports both 1.5V and 1.8V I/O supply
• HSTL Inputs and Variable Drive HSTL Output Buffers
• Available in 165-Ball FBGA Package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free Packages
• JTAG Compatible Test Access Port
• Phase Locked Loop PLL for Accurate Data Placement

Configurations

With Read Cycle Latency of cycles CY7C12411KV18 4M x 8 CY7C12561KV18 4M x 9 CY7C12431KV18 2M x 18 CY7C12451KV18 1M x 36

Functional Description

The CY7C12411KV18, CY7C12561KV18, CY7C12431KV18, and CY7C12451KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words CY7C12411KV18 , 9-bit words CY7C12561KV18 , 18-bit words CY7C12431KV18 , or 36-bit words CY7C12451KV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus “turnarounds”.

Depth expansion is accomplished with port selects, which
enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

These devices are down bonded from the 65nm 72M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and the same JTAG ID code as the equivalent 72M device options. For details refer to the application note AN53189, 65nm Technology InterimQDRII+/DDRII+ SRAM device family description.

Table Selection Guide
450 MHz

Max Operating Frequency 450

Max Operating Current x8 760
x9 760
x18 780
x36 1100
400 MHz 400 690 710 1000
375 MHz 375 660 680 950
333 MHz 333 600 620 850

Unit

MHz mA

Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
TAP Registers 13 TAP Instruction Set 13 TAP Controller State 15 TAP Controller Block 16 TAP Electrical Characteristics 16 TAP AC Switching Characteristics 17 TAP Timing and Test Conditions 17 Identification Register Definitions 18 Scan Register Sizes 18 Instruction 18 Boundary Scan Order 19 Power Up Sequence in QDR II+ SRAM 20 Power Up Sequence 20 PLL 20 Maximum 21 Operating Range 21 Neutron Soft Error 21 Electrical Characteristics 21 DC Electrical 21 AC Electrical 22 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence 25 Ordering Information 26 Package Diagram 26 Document History 27 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support....................... 28 Products 28 PSoC Solutions 28

Page 4 of 28 [+] Feedback

CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18

Pin Configuration

The pin configuration for CY7C12411KV18, CY7C12561KV18, CY7C12431KV18, and CY7C12451KV18 follow.[2]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C12411KV18 4M x 8

CQ NC/72M

WPS NWS1

K NC/144M RPS

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

QVLD

CY7C12561KV18 4M x 9

CQ NC/72M

K NC/144M RPS

A NC/288M K

BWS0

VDDQ

VDDQ

VDDQ

VDDQ
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code
400 CY7C12451KV18-400BZC

CY7C12451KV18-400BZXC

Package Diagram

Package Type

Operating Range
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial
165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180-*C

Page 26 of 28 [+] Feedback

CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18

Document History Page

Document Title 36-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency Document Number 001-53192

Orig. Of Change

Submission Date

Description Of Change
** 2702761 VKN/PYRS 05/06/2009 New data sheet
*A 2747635 VKN/AESA 08/03/2009 Converted from preliminary to final For 450 MHz speed, changed tCO, tCCQO, tCHZ from 370ps to 450ps and tDOH, tCQOH, tCLZ from -370ps to -450ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information
*B 2761928
09/10/2009 Post to external web.
*C 2767155
09/23/2009 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer
*D 2855911
01/18/2010 Included “CY7C12451KV18-400BZXC” part in the Ordering information table Updated package outline diagram

Page 27 of 28 [+] Feedback

CY7C12411KV18, CY7C12561KV18 CY7C12431KV18, CY7C12451KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 28 of 28

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

More datasheets: B48621A4605Q006 | 85100036 | 85100037 | 85100434 | 85100435 | 85100436 | 85100536 | 2562 | 1733 | CY7C12451KV18-400BZXC

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C12451KV18-400BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C12451KV18-400BZC 507941