CY7C1292DV18-167BZC

CY7C1292DV18-167BZC Datasheet

CY7C1292DV18 CY7C1294DV18

Part	Datasheet
CY7C1292DV18-167BZC	CY7C1292DV18-167BZC (pdf)

Related Parts	Information
CY7C1294DV18-167BZC	CY7C1294DV18-167BZC

PDF Datasheet Preview
CY7C1292DV18 CY7C1294DV18 9-Mbit QDR- II SRAM 2-Word Burst Architecture Functional Description • Separate Independent Read and Write data ports Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate DDR interfaces on both Read and Write ports data transferred at 500 MHz 250 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock-skew and flight-time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in x 18 and x 36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD • Available in 165-ball FBGA package 13 x 15 x mm • Offered in both lead-free and non-lead free packages • Variable drive HSTL output buffers • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate DDR interfaces. Each address location is associated with two 18-bit words CY7C1292DV18 or 36-bit words CY7C1294DV18 that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations CY7C1292DV18 512K x 18 CY7C1294DV18 256K x 36 Selection Guide Maximum Operating Frequency Maximum Operating Current 250 MHz 250 600 200 MHz 200 550 167 MHz 167 500 Unit MHz mA Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C1292DV18 CY7C1294DV18 Logic Block Diagram CY7C1292DV18 D[17:0] 18 A 17:0 18 Address Register Write Reg Write Reg Address Register 18 A 17:0 Write Add. Decode Read Add. Decode Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1292DV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1294DV18-167BZC CY7C1292DV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1294DV18-167BZXC CY7C1292DV18-167BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1294DV18-167BZI CY7C1292DV18-167BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1294DV18-167BZXI 200 CY7C1292DV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1294DV18-200BZC CY7C1292DV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1294DV18-200BZXC CY7C1292DV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1294DV18-200BZI CY7C1292DV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1294DV18-200BZXI 250 CY7C1292DV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1294DV18-250BZC CY7C1292DV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1294DV18-250BZXC CY7C1292DV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1294DV18-250BZI CY7C1292DV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free CY7C1294DV18-250BZXI Page 21 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Package Diagram 165 FBGA 13 x 15 x MM BB165D/BW165D 165-ball FBGA 13 x 15 x mm 51-85180 BOTTOM VIEW TOP VIEW TOP VIEW BOTTOM VIEWPIN 1 CORNER PIN 1 CORNER Replaced Package Name column with Package Diagram in the Ordering Information table. Updated the Ordering Information Table. Page 23 of 23 [+] Feedback

PDF Datasheet Preview

CY7C1292DV18 CY7C1294DV18
9-Mbit QDR- II SRAM 2-Word Burst Architecture

Functional Description
• Separate Independent Read and Write data ports

Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate DDR interfaces on both Read and

Write ports data transferred at 500 MHz 250 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize clock-skew and flight-time mismatches
• Echo clocks CQ and CQ simplify data capture in high-speed systems
• Single multiplexed address input bus latches address inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x 18 and x 36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD
• Available in 165-ball FBGA package 13 x 15 x mm
• Offered in both lead-free and non-lead free packages
• Variable drive HSTL output buffers
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate DDR interfaces. Each address location is associated with two 18-bit words CY7C1292DV18 or 36-bit words CY7C1294DV18 that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1292DV18 512K x 18 CY7C1294DV18 256K x 36

Selection Guide

Maximum Operating Frequency Maximum Operating Current
250 MHz 250 600
200 MHz 200 550
167 MHz 167 500

Unit MHz mA

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C1292DV18 CY7C1294DV18

Logic Block Diagram CY7C1292DV18

D[17:0] 18

A 17:0 18

Address Register

Write Reg

Write Reg

Address Register
18 A 17:0

Write Add. Decode Read Add. Decode
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1292DV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1294DV18-167BZC

CY7C1292DV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1294DV18-167BZXC

CY7C1292DV18-167BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1294DV18-167BZI

CY7C1292DV18-167BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1294DV18-167BZXI
200 CY7C1292DV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1294DV18-200BZC

CY7C1292DV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1294DV18-200BZXC

CY7C1292DV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1294DV18-200BZI

CY7C1292DV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1294DV18-200BZXI
250 CY7C1292DV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1294DV18-250BZC

CY7C1292DV18-250BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1294DV18-250BZXC

CY7C1292DV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1294DV18-250BZI

CY7C1292DV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free

CY7C1294DV18-250BZXI

Page 21 of 23 [+] Feedback

CY7C1292DV18 CY7C1294DV18

Package Diagram
165 FBGA 13 x 15 x MM BB165D/BW165D 165-ball FBGA 13 x 15 x mm 51-85180

BOTTOM VIEW

TOP VIEW TOP VIEW

BOTTOM VIEWPIN 1 CORNER PIN 1 CORNER
Replaced Package Name column with Package Diagram in the Ordering

Information table.
Updated the Ordering Information Table.

Page 23 of 23 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1292DV18-167BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1292DV18-167BZC 507939