CY7C12681KV18-450BZXC

CY7C12681KV18-450BZXC Datasheet

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18

Part	Datasheet
CY7C12681KV18-450BZXC	CY7C12681KV18-450BZXC (pdf)

Related Parts	Information
CY7C12681KV18-400BZXC	CY7C12681KV18-400BZXC
CY7C12681KV18-400BZC	CY7C12681KV18-400BZC
CY7C12701KV18-400BZXC	CY7C12701KV18-400BZXC

PDF Datasheet Preview
CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency • 36-Mbit density 4 M x 8, 4 M x 9, 2 M x 18, 1 M x 36 • 550 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double data rate DDR interfaces data transferred at 1100 MHz at 550 MHz • Available in clock cycle latency • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo clocks CQ and CQ simplify data capture in high speed systems • Data valid pin QVLD to indicate valid data on the output • Synchronous internally self-timed writes • DDR II+ operates with cycle read latency when DOFF is asserted HIGH • Operates similar to DDR I device with 1 Cycle Read Latency when DOFF is asserted LOW • Core VDD = V ± V I/O VDDQ = V to VDD[1] Supports both V and V I/O supply • HSTL inputs and variable drive HSTL output buffers • Available in 165-ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free Packages • JTAG compatible test access port • Phase locked loop PLL for accurate data placement Configurations With Read Cycle Latency of cycles CY7C12661KV18 4 M x 8 CY7C12771KV18 4 M x 9 CY7C12681KV18 2 M x 18 CY7C12701KV18 1 M x 36 Functional Description The CY7C12661KV18, CY7C12771KV18, CY7C12681KV18, and CY7C12701KV18 are V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C12661KV18 , 9-bit words CY7C12771KV18 , 18-bit words CY7C12681KV18 , or 36-bit words CY7C12701KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. These devices are down bonded from the 65 nm 72 M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and the same JTAG ID code as the equivalent 72 M device options. For details refer to the application note AN53189, 65 nm Technology InterimQDRII+/DDRII+ SRAM device family description. Table Selection Guide 550 MHz Max operating frequency Max operating current x 8 740 x 9 740 x 18 760 x 36 970 500 MHz 500 690 700 890 450 MHz 450 630 650 820 400 MHz 400 580 590 750 Unit MHz mA Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = V to VDD. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C12661KV18 CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 A 20:0 K DOFF VREF R/W NWS[1:0] Address Register CLK Gen. Control Logic Write Reg Write Reg 2M x 8 Array 2M x 8 Array Read Data Reg. 16 8 Read/Write/Deselect Sequence 25 Ordering Information 26 Ordering Code Definitions 26 Package Diagram 27 Acronyms 28 Document Conventions 28 Units of Measure 28 Document History Page 29 Sales, Solutions, and Legal Information 30 Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30 Page 4 of 30 [+] Feedback CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 Pin Configuration The pin configuration for CY7C12661KV18, CY7C12771KV18, CY7C12681KV18, and CY7C12701KV18 follow. [2] 165-ball FBGA 13 x 15 x mm Pinout CY7C12661KV18 4 M x 8 CQ NC/72M NWS1 K NC/144M LD A NC/288M K NWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ QVLD CY7C12771KV18 4 M x 9 CQ NC/72M K NC/144M LD A NC/288M K BWS0 VDDQ VDDQ Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code Package Diagram Package Type Operating Range 450 CY7C12681KV18-450BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free Commercial 400 CY7C12681KV18-400BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C12681KV18-400BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free CY7C12701KV18-400BZXC Ordering Code Definitions CY7C 12XX1 K V18 - XXX C Temperature range C = Commercial Package Type XXX = BZX or BZ BZX = 165-ball FPBGA Pb-free BZ = 165-ball FPBGA Speed Grade 450 MHz / 400 MHz V18 = V Process Technology 65 nm Part Identifier = 12681 / 12701 CY7C = Cypress SRAMs Page 26 of 30 [+] Feedback CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 Package Diagram Figure 165-ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180 C Page 27 of 30 [+] Feedback Acronyms Acronym CE CEN CMOS FPBGA I/O JTAG NoBL OE PLL SRAM TCK TMS TDI TDO TQFP WE Description chip enable clock enable complementary metal oxide semiconductor fine-pitch ball grid array input/output Joint Test Action Group No Bus Latency output enable phase locked loop static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 Document Conventions Units of Measure Symbol ns V µA mA ms mm MHz pF W °C Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds milli meter Mega Hertz pico Farad Watts degree Celcius Page 28 of 30 [+] Feedback CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 Document History Page Document Title 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency Document Number 001-53195 ECN NO. Submission Date Orig. Of Change Description Of Change * 2702761 05/06/2009 VKN/PYRS New Data Sheet A 2855911 01/18/2010 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer Updated Ordering information table Updated package outline diagram Added Contents. B 2868256 01/28/2010 Included “CY7C12681KV18-400BZC” and “CY7C12701KV18-400BZXC” part in the Ordering Information table. C 2877876 02/12/2010 Converted from Preliminary to final, Included “CY7C12681KV18-450BZXC” part in the Ordering Information table. D 3044999 10/01/2010 Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. Page 29 of 30 [+] Feedback CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 30 of 30 [+] Feedback

PDF Datasheet Preview

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18
36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency
36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency
• 36-Mbit density 4 M x 8, 4 M x 9, 2 M x 18, 1 M x 36
• 550 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate DDR interfaces
data transferred at 1100 MHz at 550 MHz
• Available in clock cycle latency
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high speed
systems
• Data valid pin QVLD to indicate valid data on the output
• Synchronous internally self-timed writes
• DDR II+ operates with cycle read latency when DOFF is
asserted HIGH
• Operates similar to DDR I device with 1 Cycle Read Latency
when DOFF is asserted LOW
• Core VDD = V ± V I/O VDDQ = V to VDD[1]

Supports both V and V I/O supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free Packages
• JTAG compatible test access port
• Phase locked loop PLL for accurate data placement

Configurations

With Read Cycle Latency of cycles CY7C12661KV18 4 M x 8 CY7C12771KV18 4 M x 9 CY7C12681KV18 2 M x 18 CY7C12701KV18 1 M x 36

Functional Description

The CY7C12661KV18, CY7C12771KV18, CY7C12681KV18, and CY7C12701KV18 are V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C12661KV18 , 9-bit words CY7C12771KV18 , 18-bit words CY7C12681KV18 , or 36-bit words CY7C12701KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. These devices are down bonded from the 65 nm 72 M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and the same JTAG ID code as the equivalent 72 M device options. For details refer to the application note AN53189, 65 nm Technology InterimQDRII+/DDRII+ SRAM device family description.

Table Selection Guide
550 MHz

Max operating frequency

Max operating current x 8 740
x 9 740
x 18 760
x 36 970
500 MHz 500 690 700 890
450 MHz 450 630 650 820
400 MHz 400 580 590 750

Unit

MHz mA

Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = V to VDD.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C12661KV18

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18

A 20:0

K DOFF

VREF R/W NWS[1:0]

Address Register

CLK Gen.

Control Logic

Write Reg

Write Reg
2M x 8 Array 2M x 8 Array

Read Data Reg. 16 8
Read/Write/Deselect Sequence 25 Ordering Information 26
Ordering Code Definitions 26 Package Diagram 27 Acronyms 28 Document Conventions 28

Units of Measure 28 Document History Page 29 Sales, Solutions, and Legal Information 30

Worldwide Sales and Design Support 30 Products 30 PSoC Solutions 30

Page 4 of 30 [+] Feedback

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18

Pin Configuration

The pin configuration for CY7C12661KV18, CY7C12771KV18, CY7C12681KV18, and CY7C12701KV18 follow. [2]
165-ball FBGA 13 x 15 x mm Pinout

CY7C12661KV18 4 M x 8

CQ NC/72M

NWS1

K NC/144M LD

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

QVLD

CY7C12771KV18 4 M x 9

CQ NC/72M

K NC/144M LD

A NC/288M K

BWS0

VDDQ

VDDQ
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
450 CY7C12681KV18-450BZXC
51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free Commercial
400 CY7C12681KV18-400BZC
51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C12681KV18-400BZXC
51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free

CY7C12701KV18-400BZXC
Ordering Code Definitions CY7C 12XX1 K V18 - XXX C

Temperature range C = Commercial Package Type XXX = BZX or BZ BZX = 165-ball FPBGA Pb-free BZ = 165-ball FPBGA Speed Grade 450 MHz / 400 MHz V18 = V Process Technology 65 nm Part Identifier = 12681 / 12701 CY7C = Cypress SRAMs

Page 26 of 30 [+] Feedback

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18

Package Diagram

Figure 165-ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180 *C

Page 27 of 30 [+] Feedback

Acronyms

Acronym CE CEN CMOS FPBGA I/O JTAG NoBL OE PLL SRAM TCK TMS TDI TDO TQFP WE

Description chip enable clock enable complementary metal oxide semiconductor fine-pitch ball grid array input/output Joint Test Action Group No Bus Latency output enable phase locked loop static random access memory test clock test mode select test data-in test data-out thin quad flat pack write enable

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18

Document Conventions

Units of Measure

Symbol ns V µA mA ms mm MHz pF W °C

Unit of Measure nano seconds Volts micro Amperes milli Amperes milli seconds milli meter Mega Hertz pico Farad Watts degree Celcius

Page 28 of 30 [+] Feedback

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18

Document History Page

Document Title 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency Document Number 001-53195

ECN NO.

Submission Date

Orig. Of Change

Description Of Change
** 2702761 05/06/2009 VKN/PYRS New Data Sheet
*A 2855911 01/18/2010
Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer Updated Ordering information table Updated package outline diagram Added Contents.
*B 2868256
01/28/2010 Included “CY7C12681KV18-400BZC” and “CY7C12701KV18-400BZXC” part in the Ordering Information table.
*C 2877876
02/12/2010 Converted from Preliminary to final, Included “CY7C12681KV18-450BZXC” part in the Ordering Information table.
*D 3044999
10/01/2010 Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template.

Page 29 of 30 [+] Feedback

CY7C12661KV18, CY7C12771KV18 CY7C12681KV18, CY7C12701KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 30 of 30
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C12681KV18-450BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C12681KV18-450BZXC 507937