CY7C1250KV18-450BZXC

CY7C1250KV18-450BZXC Datasheet

CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18

Part	Datasheet
CY7C1250KV18-450BZXC	CY7C1250KV18-450BZXC (pdf)

Related Parts	Information
CY7C1250KV18-400BZI	CY7C1250KV18-400BZI
CY7C1248KV18-450BZXC	CY7C1248KV18-450BZXC

PDF Datasheet Preview
CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency Configurations • 36 Mbit density 4 M x 8, 4 M x 9, 2 M x 18, 1 M x 36 • 450 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double data rate DDR interfaces data transferred at 900 MHz at 450 MHz With Read Cycle Latency of Cycles CY7C1246KV18 4 M x 8 CY7C1257KV18 4 M x 9 CY7C1248KV18 2 M x 18 CY7C1250KV18 1 M x 36 • Available in clock cycle latency Functional Description • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo clocks CQ and CQ simplify data capture in high speed systems • Data valid pin QVLD to indicate valid data on the output • Synchronous internally self-timed writes • DDR II+ operates with cycle read latency when DOFF is asserted HIGH • Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW • Core VDD = V ± V I/O VDDQ = V to VDD[1] Supports both V and V I/O supply • HSTL inputs and variable drive HSTL output buffers • Available in 165-ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port The CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 are V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C1246KV18 , 9-bit words CY7C1257KV18 , 18-bit words CY7C1248KV18 , or 36-bit words CY7C1250KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. • Phase-locked loop PLL for accurate data placement Table Selection Guide Description Maximum operating frequency Maximum operating current x8 x9 x 18 x 36 450 MHz 450 590 600 760 400 MHz 400 540 550 690 375 MHz 375 520 530 660 333 MHz 333 480 490 600 Unit MHz mA Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = V to VDD. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1246KV18 CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 A 20:0 K DOFF VREF R/W NWS[1:0] Address Register CLK Gen. Control Logic Write Reg Write Reg 2M x 8 Array 2M x 8 Array Read Data Reg. 16 8 Logic Block Diagram CY7C1257KV18 Write Add. Decode Read Add. Decode Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 DC Electrical Characteristics 21 AC Electrical Characteristics 23 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence 25 Ordering Information 26 Ordering Code Definitions 26 Package Diagram 27 Document History Page 28 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28 Page 4 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Pin Configuration The pin configuration for CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 follows.[2] 165-ball FBGA 13 x 15 x mm pinout CY7C1246KV18 4 M x 8 CQ NC/72M NWS1 K NC/144M LD A NC/288M K NWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ QVLD CY7C1257KV18 4 M x 9 CQ NC/72M K NC/144M LD A NC/288M K BWS0 VDDQ VDDQ VDDQ VDDQ Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Speed MHz Ordering Code 400 CY7C1250KV18-400BZI CY7C1248KV18-400BZC CY7C1248KV18-400BZXC CY7C1250KV18-400BZC CY7C1250KV18-400BZXC 450 CY7C1248KV18-450BZXC CY7C1250KV18-450BZXC Ordering Code Definitions Package Diagram Package Type Operating Range 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial Commercial 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free Commercial CY 7C 12XX K V18 - XXX BZ X C Temperature Range C = Commercial = 0 C to +70 C I = Industrial = C to +85 C X = Pb-free X Absent = Leaded Package Type BZ = 165-ball FPBGA Speed Grade XXX = 450 MHz / 400 MHz V18 = V VDD Process Technology 65 nm 12XX = 1248 or 1250 = Part Identifier Marketing Code 7C = SRAMs Company ID CY = Cypress Page 26 of 28 [+] Feedback Package Diagram CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Figure 165-ball FBGA 13 x 15 x mm , 51-85180 51-85180 C Page 27 of 28 [+] Feedback CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18 Document History Page Document Title 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency Document Number 001-57834 Submission Date Orig. of Change Description of Change * 2816636 VKN/AESA 11/30/09 New data sheet A 3068547 10/22/2010 Converted from Preliminary to Final. Added Ordering Code Definitions. Updated Package Diagram. Minor edits and updated in new template. B 3181270 SHTC 02/24/2011 Added CY7C1248KV18-400BZC, CY7C1250KV18-400BZC, and CY7C1250KV18-400BZI in Ordering Information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction1, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 28 of 28 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18
36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency
36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency

Configurations
• 36 Mbit density 4 M x 8, 4 M x 9, 2 M x 18, 1 M x 36
• 450 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate DDR interfaces
data transferred at 900 MHz at 450 MHz

With Read Cycle Latency of Cycles CY7C1246KV18 4 M x 8 CY7C1257KV18 4 M x 9 CY7C1248KV18 2 M x 18 CY7C1250KV18 1 M x 36
• Available in clock cycle latency

Functional Description
• Two input clocks K and K for precise DDR timing SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high speed systems
• Data valid pin QVLD to indicate valid data on the output
• Synchronous internally self-timed writes
• DDR II+ operates with cycle read latency when DOFF is
asserted HIGH
• Operates similar to DDR I device with 1 cycle read latency when

DOFF is asserted LOW
• Core VDD = V ± V I/O VDDQ = V to VDD[1]

Supports both V and V I/O supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port

The CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 are V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C1246KV18 , 9-bit words CY7C1257KV18 , 18-bit words CY7C1248KV18 , or 36-bit words CY7C1250KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
• Phase-locked loop PLL for accurate data placement Table Selection Guide

Description Maximum operating frequency Maximum operating current
x8 x9 x 18 x 36
450 MHz 450 590 600 760
400 MHz 400 540 550 690
375 MHz 375 520 530 660
333 MHz 333 480 490 600

Unit MHz mA

Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = V to VDD.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1246KV18

CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18

A 20:0

K DOFF

VREF R/W NWS[1:0]

Address Register

CLK Gen.

Control Logic

Write Reg

Write Reg
2M x 8 Array 2M x 8 Array

Read Data Reg. 16 8

Logic Block Diagram CY7C1257KV18

Write Add. Decode Read Add. Decode
Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 Electrical Characteristics 21 DC Electrical Characteristics 21 AC Electrical Characteristics 23 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence 25 Ordering Information 26 Ordering Code Definitions 26 Package Diagram 27 Document History Page 28 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28

Page 4 of 28 [+] Feedback

CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18

Pin Configuration

The pin configuration for CY7C1246KV18, CY7C1257KV18, CY7C1248KV18, and CY7C1250KV18 follows.[2]
165-ball FBGA 13 x 15 x mm pinout

CY7C1246KV18 4 M x 8

CQ NC/72M

NWS1

K NC/144M LD

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

QVLD

CY7C1257KV18 4 M x 9

CQ NC/72M

K NC/144M LD

A NC/288M K

BWS0

VDDQ

VDDQ

VDDQ

VDDQ
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at

Speed MHz
Ordering Code
400 CY7C1250KV18-400BZI

CY7C1248KV18-400BZC

CY7C1248KV18-400BZXC

CY7C1250KV18-400BZC

CY7C1250KV18-400BZXC
450 CY7C1248KV18-450BZXC

CY7C1250KV18-450BZXC
Ordering Code Definitions

Package Diagram

Package Type

Operating Range
51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

Commercial
165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free
165-ball Fine Pitch Ball Grid Array 13 x 15 x mm
165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free
51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-free Commercial

CY 7C 12XX K V18 - XXX BZ X C

Temperature Range C = Commercial = 0 C to +70 C I = Industrial = C to +85 C X = Pb-free X Absent = Leaded Package Type BZ = 165-ball FPBGA Speed Grade XXX = 450 MHz / 400 MHz V18 = V VDD Process Technology 65 nm 12XX = 1248 or 1250 = Part Identifier Marketing Code 7C = SRAMs Company ID CY = Cypress

Page 26 of 28 [+] Feedback

Package Diagram

CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18

Figure 165-ball FBGA 13 x 15 x mm , 51-85180
51-85180 *C

Page 27 of 28 [+] Feedback

CY7C1246KV18, CY7C1257KV18 CY7C1248KV18, CY7C1250KV18

Document History Page

Document Title 36-Mbit DDR II+ SRAM 2-Word Burst Architecture Cycle Read Latency Document Number 001-57834

Submission Date

Orig. of Change

Description of Change
** 2816636 VKN/AESA 11/30/09 New data sheet
*A 3068547
10/22/2010
Converted from Preliminary to Final. Added Ordering Code Definitions. Updated Package Diagram. Minor edits and updated in new template.
*B 3181270 SHTC
02/24/2011 Added CY7C1248KV18-400BZC, CY7C1250KV18-400BZC, and CY7C1250KV18-400BZI in Ordering Information

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction1, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 28 of 28

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1250KV18-450BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1250KV18-450BZXC 507931