CY7C11681KV18-400BZC

CY7C11681KV18-400BZC Datasheet

CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

Part	Datasheet
CY7C11681KV18-400BZC	CY7C11681KV18-400BZC (pdf)

Related Parts	Information
CY7C11681KV18-400BZXC	CY7C11681KV18-400BZXC
CY7C11681KV18-450BZC	CY7C11681KV18-450BZC
CY7C11681KV18-450BZXC	CY7C11681KV18-450BZXC
CY7C11701KV18-400BZXC	CY7C11701KV18-400BZXC

PDF Datasheet Preview
CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture Cycle Read Latency 18-Mbit DDR II+ SRAM Two-Burst Architecture Cycle Read Latency • 18-Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36 • 550 MHz clock for high bandwidth • 2-word burst for reducing address bus frequency • Double data rate DDR interfaces data transferred at 1100 MHz at 550 MHz • Available in clock cycle latency • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo clocks CQ and CQ simplify data capture in high-speed systems • Data valid pin QVLD to indicate valid data on the output • Synchronous internally self-timed writes • DDR II+ operates with cycle read latency when DOFF is asserted HIGH • Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW • Core VDD = V ± V I/O VDDQ = V to VDD[1] Supports both V and V I/O supply • HSTL inputs and variable drive HSTL output buffers • Available in 165-Ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Phase-locked loop PLL for accurate data placement Configurations With Read cycle latency of cycles CY7C11661KV18 2 M x 8 CY7C11771KV18 2 M x 9 CY7C11681KV18 1 M x 18 CY7C11701KV18 512 K x 36 Functional Description The CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 are V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C11661KV18 , 9-bit words CY7C11771KV18 , 18-bit words CY7C11681KV18 , or 36-bit words CY7C11701KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Table Selection Guide Maximum operating frequency Maximum operating current 550 MHz 500 MHz 450 MHz 400 MHz Unit 550 500 450 400 MHz x8 740 690 630 580 mA x9 740 690 630 580 x18 760 700 650 590 x36 970 890 820 750 Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = V to VDD. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C11661KV18 CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 A 19:0 K DOFF VREF R/W NWS[1:0] Address Register CLK Gen. Control Logic Write Reg Write Reg 1 M x 8 Array 1 M x 8 Array Read Data Reg. 16 8 Logic Block Diagram CY7C11771KV18 Write Add. Decode Read Add. Decode Output Logic Power-up Sequence 16 PLL Constraints 16 Maximum Ratings 17 Operating Range 17 Neutron Soft Error Immunity 17 Electrical Characteristics 17 DC Electrical Characteristics 17 AC Electrical Characteristics 19 Capacitance 19 Thermal Resistance 19 Switching Characteristics 20 Switching Waveforms 21 Read/Write/Deselect Sequence 21 Ordering Information 22 Ordering Code Definitions 22 Package Diagram 23 Acronyms 24 Document Conventions 24 Units of Measure 24 Document History Page 25 Sales, Solutions, and Legal Information 26 Worldwide Sales and Design Support 26 Products 26 PSoC Solutions 26 Page 4 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Functional Overview The CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of two and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS, the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock K . All synchronous input and output timing are referenced from the rising edge of the input clocks K and K . All synchronous data inputs D[x:0] pass through input registers controlled by the rising edge of the input clocks K and K . All synchronous data outputs Q[x:0] pass through output registers controlled by the rising edge of the input clocks K and K . All synchronous control R/W, LD, NWS[X:0], BWS[X:0] inputs pass through input registers controlled by the rising edge of the input clock K . CY7C11681KV18 is described in the following sections. The same basic descriptions apply to CY7C11661KV18, CY7C11771KV18, and CY7C11701KV18. Read Operations The CY7C11681KV18 is organized internally as two arrays of 512 K x Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock K . The address presented to the address inputs is stored in the read address register. Following the next two K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid ns from the rising edge of the input clock K and K . To maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock K . When read access is deselected, the CY7C11681KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the output following the next rising edge of the negative input clock K . This enables a transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock K . The address presented to address inputs is stored in the write address register. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock K the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock K . Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K . When the write access is deselected, the device ignores all inputs after the pending write operations have been completed. Byte Write Operations Byte write operations are supported by the CY7C11681KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation. DDR Operation The CY7C11681KV18 enables high performance operation through high clock frequencies achieved through pipelining and DDR mode of operation. The CY7C11681KV18 requires two No Operation NOP cycle during transition from a read to a write cycle. At higher frequencies, some applications require third NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information is stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read s , the stored data from the earlier write is written into the SRAM array. This is called a Posted write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers. Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 with VDDQ = V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the DDR II+ to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page Page 5 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Valid Data Indicator QVLD is provided on the DDR II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the PLL is locked after Application Example Figure 1 shows two DDR II+ used in an application. Figure Application Example 20 of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR I mode with one cycle latency and a longer access time . For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+. Addresses MASTER CPU or ASIC R/W Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2 R = 250ohms SRAM#1 CQ/CQ A LD R/W BWS K DQ A LD SRAM#2 R/W BWS ZQ CQ/CQ KK R = 250ohms Page 6 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Truth Table The truth table for the CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 follows.[2, 3, 4, 5, 6, 7] Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code CY7C11681KV18-450BZC 450 CY7C11681KV18-450BZXC CY7C11701KV18-450BZXC CY7C11681KV18-400BZC 400 CY7C11701KV18-400BZXC CY7C11681KV18-400BZXC Package Diagram Package Type 165-Ball FBGA 13 x 15 x mm 51-85180 165-Ball FBGA 13 x 15 x mm Pb-free 165-Ball FBGA 13 x 15 x mm Pb-free 165-Ball FBGA 13 x 15 x mm 51-85180 165-Ball FBGA 13 x 15 x mm Pb-free Operating Range Commercial Commercial Ordering Code Definitions CY 7 C 11XXX K V18 - XXX BZ X, C Package Type BZ = TSOP, X = Pb-free, Temperature Grade C = Commercial Maximum operating frequency Voltage V Technology CMOS Marketing Code 7 = SRAM Company ID CY = Cypress Page 22 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180 *C Page 23 of 26 [+] Feedback Acronyms Acronym DDR FBGA HSTL JEDEC JTAG LMBU LSBU PLL QDR SEL TAP TCK TDI TDO TMS Description double data rate fine-pitch ball grid array high speed transceiver logic joint electron device engineering council joint test action group logical multiple-bit upset logical single-bit upset phase-locked loop quad data rate single event latch-up test access port test clock test data in test data out test mode select Document Conventions Units of Measure Symbol °C MHz µA mA ns pF V W Unit of Measure degree Celsius megahertz micro amperes milliamperes nano seconds ohms pico Farad volts watts CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Page 24 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Document History Page Document Title 18-Mbit DDR II+ SRAM Two-Word Burst Architecture Cycle Read Latency Document Number 001-53199 Orig of Change Submission Date Description of Change 2702744 VKN/PYRS 05/06/09 New datasheet Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information 2761928 09/10/2009 Post to external web 2767155 VKN 09/23/2009 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer 2785104 VKN 10/16/2009 Updated Ordering information table 2855911 VKN 01/18/2010 Included “CY7C11701KV18-400BZXC” part in the Ordering information table Updated package outline diagram Added Contents. 2896003 03/19/2010 Removed inactive parts from Ordering Information. Updated package diagram. Updated links in Sales, Solutions, and Legal Information. 2950522 CS/NJY 08/16/10 Added partnumber CY7C11701KV18-450BZXC and CY7C11701KV18-400BZXC to the ordering information table. Template update. Added ordering code definitions, acronyms, and units of measure. 3056557 10/12/2010 Added new CY7C11681KV18-400BZXC part number to the Ordering Information table. Page 25 of 26 [+] Feedback CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 26 of 26 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18
18-Mbit DDR II+ SRAM Two-Word Burst Architecture Cycle Read Latency
18-Mbit DDR II+ SRAM Two-Burst Architecture Cycle Read Latency
• 18-Mbit density 2 M x 8, 2 M x 9, 1 M x 18, 512 K x 36
• 550 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate DDR interfaces
data transferred at 1100 MHz at 550 MHz
• Available in clock cycle latency
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high-speed
systems
• Data valid pin QVLD to indicate valid data on the output
• Synchronous internally self-timed writes
• DDR II+ operates with cycle read latency when DOFF is
asserted HIGH
• Operates similar to DDR I device with 1 cycle read latency when

DOFF is asserted LOW
• Core VDD = V ± V I/O VDDQ = V to VDD[1]

Supports both V and V I/O supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-Ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Phase-locked loop PLL for accurate data placement

Configurations

With Read cycle latency of cycles CY7C11661KV18 2 M x 8 CY7C11771KV18 2 M x 9 CY7C11681KV18 1 M x 18 CY7C11701KV18 512 K x 36

Functional Description

The CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 are V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words CY7C11661KV18 , 9-bit words CY7C11771KV18 , 18-bit words CY7C11681KV18 , or 36-bit words CY7C11701KV18 that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Table Selection Guide

Maximum operating frequency Maximum operating current
550 MHz
500 MHz
450 MHz
400 MHz

Unit
550 500 450 400 MHz
x8 740 690 630 580 mA x9 740 690 630 580 x18 760 700 650 590 x36 970 890 820 750

Note The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = V to VDD.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C11661KV18

CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

A 19:0

K DOFF

VREF R/W NWS[1:0]

Address Register

CLK Gen.

Control Logic

Write Reg

Write Reg
1 M x 8 Array 1 M x 8 Array

Read Data Reg. 16 8

Logic Block Diagram CY7C11771KV18

Write Add. Decode Read Add. Decode

Output Logic
Power-up Sequence 16 PLL Constraints 16 Maximum Ratings 17 Operating Range 17 Neutron Soft Error Immunity 17 Electrical Characteristics 17 DC Electrical Characteristics 17 AC Electrical Characteristics 19 Capacitance 19 Thermal Resistance 19 Switching Characteristics 20 Switching Waveforms 21 Read/Write/Deselect Sequence 21 Ordering Information 22 Ordering Code Definitions 22 Package Diagram 23 Acronyms 24 Document Conventions 24 Units of Measure 24 Document History Page 25 Sales, Solutions, and Legal Information 26 Worldwide Sales and Design Support 26 Products 26 PSoC Solutions 26

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CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

Functional Overview

The CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of two and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS, the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock K . All synchronous input and output timing are referenced from the rising edge of the input clocks K and K . All synchronous data inputs D[x:0] pass through input registers controlled by the rising edge of the input clocks K and K . All synchronous data outputs Q[x:0] pass through output registers controlled by the rising edge of the input clocks K and K . All synchronous control R/W, LD, NWS[X:0], BWS[X:0] inputs pass through input registers controlled by the rising edge of the input clock K . CY7C11681KV18 is described in the following sections. The same basic descriptions apply to CY7C11661KV18, CY7C11771KV18, and CY7C11701KV18.

Read Operations The CY7C11681KV18 is organized internally as two arrays of 512 K x Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock K . The address presented to the address inputs is stored in the read address register. Following the next two K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid ns from the rising edge of the input clock K and K . To maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock K . When read access is deselected, the CY7C11681KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the output following the next rising edge of the negative input clock K . This enables a transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock K . The address presented to address inputs is stored in the write address register. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock K the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock K . Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K .

When the write access is deselected, the device ignores all inputs after the pending write operations have been completed.

Byte Write Operations Byte write operations are supported by the CY7C11681KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation.

DDR Operation The CY7C11681KV18 enables high performance operation through high clock frequencies achieved through pipelining and DDR mode of operation. The CY7C11681KV18 requires two No Operation NOP cycle during transition from a read to a write cycle. At higher frequencies, some applications require third NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information is stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read s , the stored data from the earlier write is written into the SRAM array. This is called a Posted write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers.

Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.

Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 and 350 with VDDQ = V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.

Echo Clocks Echo clocks are provided on the DDR II+ to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page

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[+] Feedback

CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

Valid Data Indicator QVLD is provided on the DDR II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the PLL is locked after

Application Example

Figure 1 shows two DDR II+ used in an application. Figure Application Example
20 of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR I mode with one cycle latency and a longer access time . For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+.

Addresses

MASTER

CPU or ASIC R/W

Source CLK

Source CLK

Echo Clock1/Echo Clock1

Echo Clock2/Echo Clock2

R = 250ohms

SRAM#1

CQ/CQ

A LD R/W BWS K

DQ A LD

SRAM#2

R/W BWS

ZQ CQ/CQ KK

R = 250ohms

Page 6 of 26 [+] Feedback

CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

Truth Table

The truth table for the CY7C11661KV18, CY7C11771KV18, CY7C11681KV18, and CY7C11701KV18 follows.[2, 3, 4, 5, 6, 7]
Ordering Information

Cypress offers other versions of this type of product in many different configurations and features. The following table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at and refer to the product summary page at or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code

CY7C11681KV18-450BZC
450 CY7C11681KV18-450BZXC

CY7C11701KV18-450BZXC

CY7C11681KV18-400BZC
400 CY7C11701KV18-400BZXC

CY7C11681KV18-400BZXC

Package Diagram

Package Type
165-Ball FBGA 13 x 15 x mm
51-85180 165-Ball FBGA 13 x 15 x mm Pb-free
165-Ball FBGA 13 x 15 x mm Pb-free
165-Ball FBGA 13 x 15 x mm
51-85180 165-Ball FBGA 13 x 15 x mm Pb-free

Operating Range

Commercial

Commercial
Ordering Code Definitions CY 7 C 11XXX K V18 - XXX BZ X, C

Package Type BZ = TSOP, X = Pb-free, Temperature Grade C = Commercial

Maximum operating frequency

Voltage V

Technology CMOS Marketing Code 7 = SRAM

Company ID CY = Cypress

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CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180 *C

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Acronyms

Acronym DDR FBGA HSTL JEDEC JTAG LMBU LSBU PLL QDR SEL TAP TCK TDI TDO TMS

Description double data rate fine-pitch ball grid array high speed transceiver logic joint electron device engineering council joint test action group logical multiple-bit upset logical single-bit upset phase-locked loop quad data rate single event latch-up test access port test clock test data in test data out test mode select

Document Conventions

Units of Measure

Symbol °C MHz µA mA ns pF V W

Unit of Measure degree Celsius megahertz micro amperes milliamperes nano seconds ohms pico Farad volts watts

CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

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CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

Document History Page

Document Title 18-Mbit DDR II+ SRAM Two-Word Burst Architecture Cycle Read Latency Document Number 001-53199

Orig of Change

Submission Date

Description of Change
2702744 VKN/PYRS 05/06/09 New datasheet
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information
2761928
09/10/2009 Post to external web
2767155 VKN
09/23/2009 Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Modified Ordering code disclaimer
2785104 VKN
10/16/2009 Updated Ordering information table
2855911 VKN
01/18/2010 Included “CY7C11701KV18-400BZXC” part in the Ordering information table Updated package outline diagram Added Contents.
2896003
03/19/2010 Removed inactive parts from Ordering Information. Updated package diagram. Updated links in Sales, Solutions, and Legal Information.
2950522 CS/NJY
08/16/10 Added partnumber CY7C11701KV18-450BZXC and
CY7C11701KV18-400BZXC to the ordering information table.

Template update.
Added ordering code definitions, acronyms, and units of measure.
3056557
10/12/2010 Added new CY7C11681KV18-400BZXC part number to the Ordering Information table.

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CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 26 of 26

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C11681KV18-400BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C11681KV18-400BZC 507927