CY7C11651KV18-400BZC

CY7C11651KV18-400BZC Datasheet

CY7C11611KV18, CY7C11761KV18

Part	Datasheet
CY7C11651KV18-400BZC	CY7C11651KV18-400BZC (pdf)

Related Parts	Information
CY7C11651KV18-400BZXC	CY7C11651KV18-400BZXC

PDF Datasheet Preview
CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18 18-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency 18-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency • Separate independent read and write data ports Supports concurrent transactions • 550 MHz clock for high bandwidth • 4-word burst for reducing address bus frequency • Double Data Rate DDR interfaces on both read and write ports data transferred at 1100 MHz at 550 MHz • Available in clock cycle latency • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Echo clocks CQ and CQ simplify data capture in high speed systems • Data valid pin QVLD to indicate valid data on the output • Single multiplexed address input bus latches address inputs for read and write ports • Separate port selects for depth expansion • Synchronous internally self timed writes • II+ operates with cycle read latency when DOFF is asserted HIGH • Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW • Available in x8, x9, x18, and x36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V± 0.1V I/O VDDQ = 1.4V to VDD [1] Supports both 1.5V and 1.8V I/O supply • HSTL inputs and variable drive HSTL output buffers • Available in 165-ball FBGA package 13 x 15 x mm • Offered in both Pb-free and non Pb-free packages • JTAG compatible test access port • Phase Locked Loop PLL for accurate data placement Configurations With Read cycle latency of cycles CY7C11611KV18 2M x 8 CY7C11761KV18 2M x 9 CY7C11631KV18 1M x 18 CY7C11651KV18 512K x 36 Functional Description The CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words CY7C11611KV18 , 9-bit words CY7C11761KV18 , 18-bit words CY7C11631KV18 , or 36-bit words CY7C11651KV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. These devices are down bonded from the 65 nm 72M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and JTAG ID code as the equivalent 72M device options. For details refer to the application note AN53189, 65 nm Technology Interim QDRII+/DDRII+ SRAM Device Family Description. Table Selection Guide Maximum Operating Frequency Maximum Operating Current 550 MHz 500 MHz 450 MHz 400 MHz Unit 550 500 450 400 MHz x8 900 830 760 690 mA x9 900 830 760 690 x18 920 850 780 710 x36 1310 1210 1100 1000 • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18 Logic Block Diagram CY7C11611KV18 D[7:0] A 18:0 19 Address Register K DOFF VREF WPS NWS[1:0] CLK Gen. Control Logic Write Add. Decode Read Add. Decode Test Data-Out TDO 13 Performing a TAP Reset 13 TAP Registers 13 TAP Instruction Set 13 TAP Electrical Characteristics 16 TAP AC Switching Characteristics 17 TAP Timing and Test Conditions 17 Power Up Sequence in QDR II+ SRAM 20 Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 DC Electrical Characteristics 21 AC Electrical Characteristics 22 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence [31, 32, 33] 25 Ordering Information 26 Package Diagram 26 Document History Page 27 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28 Page 4 of 28 [+] Feedback CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18 Pin Configuration The pin configuration for CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 follows.[2] 165-Ball FBGA 13 x 15 x mm Pinout CY7C11611KV18 2M x 8 CQ NC/72M WPS NWS1 K NC/144M RPS NC/36M CQ A NC/288M K NWS0 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DOFF VREF VDDQ VDDQ VDDQ VDDQ VREF VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ QVLD CY7C11761KV18 2M x 9 CQ NC/72M K NC/144M RPS NC/36M CQ A NC/288M K BWS0 VDDQ VDDQ Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at Table Ordering Information Speed MHz Ordering Code Package Diagram Package Type Operating Range 400 CY7C11651KV18-400BZC CY7C11651KV18-400BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free Package Diagram Figure 165-Ball FBGA 13 x 15 x mm , 51-85180 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R SEATING PLANE C MAX. C BOTTOM VIEW PIN 1 CORNER M C M C A B 165X 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 0.15 4X NOTES : SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC 51-85180-C Page 26 of 28 [+] Feedback CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18 Document History Page Document Title 18-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency Document Number 001-53197 Orig of Change Submission Date Description of Change * 2702744 VKN/PYRS 05/06/09 New datasheet A 2888780 VKN/NJY 03/08/10 Post to external web Converted from preliminary to final Added Contents Included Soft Error Immunity Data Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Corrected the typo in the hold timing parameters tHCDDR and tHD at 450MHz from 0.28ns to 0.22ns For 550 MHz, 500 MHz and 450 MHz, Changed Output timing parameters tCO, tCCQO, tCHZ specs to 450 ps and tDOH, tCQOH, tCLZ to -450 ps Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information Updated 165-ball package outline diagram Updated links in Sales, Solutions, and Legal Information B 2931775 VKN 05/13/10 Included “CY7C11651KV18-400BZXC” in the Ordering information table Page 27 of 28 [+] Feedback CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 28 of 28 [+] Feedback

PDF Datasheet Preview

CY7C11611KV18, CY7C11761KV18

CY7C11631KV18, CY7C11651KV18
18-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency
18-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency
• Separate independent read and write data ports Supports concurrent transactions
• 550 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double Data Rate DDR interfaces on both read and write ports
data transferred at 1100 MHz at 550 MHz
• Available in clock cycle latency
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Echo clocks CQ and CQ simplify data capture in high speed
systems
• Data valid pin QVLD to indicate valid data on the output
• Single multiplexed address input bus latches address inputs
for read and write ports
• Separate port selects for depth expansion
• Synchronous internally self timed writes
• II+ operates with cycle read latency when DOFF is
asserted HIGH
• Operates similar to QDR I device with 1 cycle read latency when

DOFF is asserted LOW
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V± 0.1V I/O VDDQ = 1.4V to VDD [1]

Supports both 1.5V and 1.8V I/O supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-ball FBGA package 13 x 15 x mm
• Offered in both Pb-free and non Pb-free packages
• JTAG compatible test access port
• Phase Locked Loop PLL for accurate data placement

Configurations

With Read cycle latency of cycles CY7C11611KV18 2M x 8 CY7C11761KV18 2M x 9 CY7C11631KV18 1M x 18 CY7C11651KV18 512K x 36

Functional Description

The CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write are latched on alternate rising edges of the input K clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words CY7C11611KV18 , 9-bit words CY7C11761KV18 , 18-bit words CY7C11631KV18 , or 36-bit words CY7C11651KV18 that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks K and K , memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

These devices are down bonded from the 65 nm 72M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and JTAG ID code as the equivalent 72M device options. For details refer to the application note AN53189, 65 nm Technology Interim QDRII+/DDRII+ SRAM Device Family Description.

Table Selection Guide

Maximum Operating Frequency Maximum Operating Current
550 MHz
500 MHz
450 MHz
400 MHz

Unit
550 500 450 400 MHz
x8 900 830 760 690 mA x9 900 830 760 690 x18 920 850 780 710 x36 1310 1210 1100 1000
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18

Logic Block Diagram CY7C11611KV18

D[7:0]

A 18:0 19

Address Register

K DOFF

VREF WPS NWS[1:0]

CLK Gen.

Control Logic

Write Add. Decode Read Add. Decode
Test Data-Out TDO 13 Performing a TAP Reset 13 TAP Registers 13 TAP Instruction Set 13 TAP Electrical Characteristics 16 TAP AC Switching Characteristics 17 TAP Timing and Test Conditions 17 Power Up Sequence in QDR II+ SRAM 20 Power Up Sequence 20 PLL Constraints 20 Maximum Ratings 21 Operating Range 21 Neutron Soft Error Immunity 21 DC Electrical Characteristics 21 AC Electrical Characteristics 22 Capacitance 23 Thermal Resistance 23 Switching Characteristics 24 Switching Waveforms 25 Read/Write/Deselect Sequence [31, 32, 33] 25 Ordering Information 26 Package Diagram 26 Document History Page 27 Sales, Solutions, and Legal Information 28 Worldwide Sales and Design Support 28 Products 28 PSoC Solutions 28

Page 4 of 28 [+] Feedback

CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18

Pin Configuration

The pin configuration for CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 follows.[2]
165-Ball FBGA 13 x 15 x mm Pinout

CY7C11611KV18 2M x 8

CQ NC/72M

WPS NWS1

K NC/144M RPS

NC/36M CQ

A NC/288M K

NWS0

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

DOFF

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VREF

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

QVLD

CY7C11761KV18 2M x 9

CQ NC/72M

K NC/144M RPS

NC/36M CQ

A NC/288M K

BWS0

VDDQ

VDDQ
Ordering Information

The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at and refer to the product summary page at

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at
Table Ordering Information

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
400 CY7C11651KV18-400BZC CY7C11651KV18-400BZXC
51-85180 165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial
165-Ball Fine Pitch Ball Grid Array 13 x 15 x mm Pb-Free

Package Diagram

Figure 165-Ball FBGA 13 x 15 x mm , 51-85180

TOP VIEW

PIN 1 CORNER
1 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P R

SEATING PLANE C

MAX. C

BOTTOM VIEW

PIN 1 CORNER

M C M C A B
165X
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R
0.15 4X

NOTES :

SOLDER PAD TYPE NON-SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0.475g JEDEC REFERENCE MO-216 / ISSUE E PACKAGE CODE BB0AC
51-85180-*C

Page 26 of 28 [+] Feedback

CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18

Document History Page

Document Title 18-Mbit II+ SRAM 4-Word Burst Architecture Cycle Read Latency Document Number 001-53197

Orig of Change

Submission Date

Description of Change
** 2702744 VKN/PYRS 05/06/09 New datasheet
*A 2888780 VKN/NJY
03/08/10
Post to external web Converted from preliminary to final Added Contents Included Soft Error Immunity Data Changed Input Capacitance CIN from 2 pF to 4 pF Changed Output Capacitance CO from 3 pF to 4 pF Corrected the typo in the hold timing parameters tHCDDR and tHD at 450MHz from 0.28ns to 0.22ns For 550 MHz, 500 MHz and 450 MHz, Changed Output timing parameters tCO, tCCQO, tCHZ specs to 450 ps and tDOH, tCQOH, tCLZ to -450 ps Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information Updated 165-ball package outline diagram Updated links in Sales, Solutions, and Legal Information
*B 2931775 VKN
05/13/10 Included “CY7C11651KV18-400BZXC” in the Ordering information table

Page 27 of 28 [+] Feedback

CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All products and company names mentioned in this document may be the trademarks of their respective holders.

Page 28 of 28
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C11651KV18-400BZC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C11651KV18-400BZC 507926