CY7C09349AV-12AC

CY7C09349AV-12AC Datasheet

CY7C09349AV CY7C09359AV

Part	Datasheet
CY7C09349AV-12AC	CY7C09349AV-12AC (pdf)

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CY7C09349AV CY7C09359AV 3.3V 4K/8K x 18 Synchronous Dual-Port Static RAM • True dual-ported memory cells which allow simultaneous access of the same memory location • Two Flow-Through/Pipelined devices 4K x 18 organization CY7C09349AV 8K x 18 organization CY7C09359AV • Three Modes Flow-Through Pipelined Burst • Pipelined output mode on both ports allows fast 83-MHz operation • 0.35-micron CMOS for optimum speed/power • High-speed clock to data access 9 and 12 ns max. • 3.3V Low operating power Active = 135 mA typical Standby = 10 µA typical • Fully synchronous interface for easier operation • Burst counters increment addresses internally Shorten cycle times Minimize bus noise Supported in Flow-Through and Pipelined modes • Dual Chip Enables for easy depth expansion • Upper and lower byte controls for bus matching • Automatic power-down • Commercial and Industrial temperature ranges • Available in 100-pin TQFP Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L CE0R CE1R FT/PipeL CLKL ADSL CNTENL CNTRSTL 1b 0b 1a 0a 0/1 b 12/13 Counter/ Address Register Decode Notes for 4K for 8K devices. I/O Control I/O Control True Dual-Ported RAM Array 0a 1a 0b 1b b 0/1 FT/PipeR Counter/ Address Register Decode 9 12/13 CLKR ADSR CNTENR CNTRSTR For the most recent information, visit the Cypress web site at Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 13, 2000 CY7C09349AV CY7C09359AV Functional Description The CY7C09349AV and CY7C09359AV are high-speed 3.3V synchronous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[2] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns pipelined . Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flowthrough mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin. Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times. Ordering Information 4K x18 3.3V Synchronous Dual-Port SRAM Speed ns Ordering Code Package Name A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 8K x18 3.3V Synchronous Dual-Port SRAM Speed ns Ordering Code Package Name A100 A100 A100 Document #: Package Diagram Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Plastic Quad Flat Pack TQFP A100 CY7C09349AV CY7C09359AV Operating Range Commercial Operating Range Commercial Industrial 51-85048-B Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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CY7C09349AV CY7C09359AV
3.3V 4K/8K x 18 Synchronous Dual-Port Static RAM
• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two Flow-Through/Pipelined devices 4K x 18 organization CY7C09349AV 8K x 18 organization CY7C09359AV
• Three Modes Flow-Through Pipelined Burst
• Pipelined output mode on both ports allows fast 83-MHz operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 9 and 12 ns max.
• 3.3V Low operating power

Active = 135 mA typical Standby = 10 µA typical
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally Shorten cycle times

Minimize bus noise

Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and lower byte controls for bus matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP

Logic Block Diagram

R/WL UBL

R/WR UBR

CE0L

CE1L

CE0R

CE1R

FT/PipeL

CLKL ADSL CNTENL CNTRSTL
1b 0b 1a 0a
0/1 b
12/13

Counter/ Address Register Decode

Notes for 4K for 8K devices.

I/O Control

I/O Control

True Dual-Ported RAM Array
0a 1a 0b 1b
b 0/1

FT/PipeR

Counter/ Address Register Decode
9 12/13

CLKR ADSR

CNTENR CNTRSTR

For the most recent information, visit the Cypress web site at

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600 November 13, 2000

CY7C09349AV CY7C09359AV

Functional Description

The CY7C09349AV and CY7C09359AV are high-speed 3.3V synchronous CMOS 4K and 8K x 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[2] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns pipelined . Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flowthrough mode data will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin.

Each port contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.
Ordering Information
4K x18 3.3V Synchronous Dual-Port SRAM

Speed ns
Ordering Code

Package Name

A100

A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
8K x18 3.3V Synchronous Dual-Port SRAM

Speed ns
Ordering Code

Package Name

A100

A100

A100

Document #:

Package Diagram

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
100-Pin Thin Plastic Quad Flat Pack TQFP A100

CY7C09349AV CY7C09359AV

Operating Range

Commercial

Operating Range

Commercial Industrial
51-85048-B

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C09349AV-12AC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C09349AV-12AC 507872