CY7C036A-15AC

CY7C036A-15AC Datasheet

CY7C026A CY7C036A

Part	Datasheet
CY7C036A-15AC	CY7C036A-15AC (pdf)

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25/0251 CY7C026A CY7C036A 16K x 16/18 Dual-Port Static RAM • True dual-ported memory cells which allow simultaneous access of the same memory location • 16K x 16 organization CY7C026A • 16K x 18 organization CY7C036A • 0.35-micron CMOS for optimum speed/power • High-speed access 12[1]/15/20 ns • Low operating power Active ICC = 180 mA typical Standby ISB3 = mA typical • Fully asynchronous operation • Automatic power-down • Expandable data bus to 32/36 bits or more using Mas- ter/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flags for port-to-port communication • Separate upper-byte and lower-byte control • Pin select for Master or Slave • Commercial and Industrial temperature ranges • Available in 100-Pin TQFP • Pin-compatible and functionally equivalent to IDT70261 Logic Block Diagram R/WL UBL R/WR UBR LBL OEL I/O Control I/O Control LBR OER Address Decode True Dual-Ported RAM Array R/WL SEML BUSYL INTL UBL LBL See page 6 for Load Conditions. for x16 devices for x18 devices. for x16 devices for x18 devices. BUSY is an output in master mode and an input in slave mode. Interrupt Semaphore Arbitration Address Decode CER OER R/WR SEMR BUSYR INTR UBR LBR For the most recent information, visit the Cypress web site at Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 CY7C026A CY7C036A Functional Description The CY7C026A and CY7C036A are low-power CMOS 16K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins Chip Enable CE , Read or Write Enable R/W , and Output Enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by the chip enable pin. The CY7C026A and CY7C036A are available in 100-pin Thin Quad Plastic Flatpack TQFP packages. Pin Configurations 100-Pin TQFP Top View I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL LBL A13L A12L A11L A10L A9L A8L A7L NC I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 Ordering Information 16K x16 Asynchronous Dual-Port SRAM Speed ns 12[1] 15 Ordering Code CY7C026A-12AC CY7C026A-15AC CY7C026A-15AI CY7C026A-20AC Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 16K x18 Asynchronous Dual-Port SRAM Speed ns 12[1] 15 Ordering Code CY7C036A-12AC CY7C036A-15AC CY7C036A-15AI CY7C036A-20AC Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Package Diagram 100-Pin Thin Plastic Quad Flat Pack TQFP A100 CY7C026A CY7C036A Operating Range Commercial Industrial Commercial Operating Range Commercial Industrial Commercial 51-85048-B Page 17 of 18 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C026A CY7C036A Document Title CY7C026A/CY7C036A 16K X 16/18 Dual-Port Static RAM Document Number 38-06046 Issue ECN NO. Date Orig. of Change Description of Change 110198 09/29/01 SZV Change from Spec number 38-00832 to 38-06046 122296 12/27/02 RBI Power up requirements added to Maximum Ratings Information Page 18 of 18

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25/0251

CY7C026A CY7C036A
16K x 16/18 Dual-Port Static RAM
• True dual-ported memory cells which allow simultaneous access of the same memory location
• 16K x 16 organization CY7C026A
• 16K x 18 organization CY7C036A
• 0.35-micron CMOS for optimum speed/power
• High-speed access 12[1]/15/20 ns
• Low operating power

Active ICC = 180 mA typical Standby ISB3 = mA typical
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-Pin TQFP
• Pin-compatible and functionally equivalent to IDT70261

Logic Block Diagram

R/WL UBL

R/WR UBR

LBL OEL

I/O Control

I/O Control

LBR OER

Address

Decode

True Dual-Ported RAM Array

R/WL SEML

BUSYL INTL UBL LBL

See page 6 for Load Conditions. for x16 devices for x18 devices. for x16 devices for x18 devices. BUSY is an output in master mode and an input in slave mode.

Interrupt Semaphore Arbitration

Address

Decode

CER OER

R/WR SEMR

BUSYR INTR UBR LBR

For the most recent information, visit the Cypress web site at

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600

CY7C026A CY7C036A

Functional Description

The CY7C026A and CY7C036A are low-power CMOS 16K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins Chip Enable CE , Read or Write Enable R/W , and Output Enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by the chip enable pin.

The CY7C026A and CY7C036A are available in 100-pin Thin Quad Plastic Flatpack TQFP packages.

Pin Configurations
100-Pin TQFP Top View

I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL LBL A13L A12L A11L A10L A9L A8L A7L

NC I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L

VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Ordering Information
16K x16 Asynchronous Dual-Port SRAM

Speed ns 12[1] 15
Ordering Code CY7C026A-12AC CY7C026A-15AC CY7C026A-15AI CY7C026A-20AC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
16K x18 Asynchronous Dual-Port SRAM

Speed ns 12[1] 15
Ordering Code CY7C036A-12AC CY7C036A-15AC CY7C036A-15AI CY7C036A-20AC

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack

Package Diagram
100-Pin Thin Plastic Quad Flat Pack TQFP A100

CY7C026A CY7C036A

Operating Range

Commercial Industrial Commercial

Operating Range

Commercial Industrial Commercial
51-85048-B

Page 17 of 18

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C026A CY7C036A

Document Title CY7C026A/CY7C036A 16K X 16/18 Dual-Port Static RAM Document Number 38-06046

Issue ECN NO. Date

Orig. of Change Description of Change
110198 09/29/01 SZV

Change from Spec number 38-00832 to 38-06046
122296 12/27/02 RBI

Power up requirements added to Maximum Ratings Information

Page 18 of 18

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C036A-15AC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C036A-15AC 507853