CY7C0241E-25AXC

CY7C0241E-25AXC Datasheet

CY7C024E, CY7C0241E CY7C025E, CY7C0251E

Part	Datasheet
CY7C0241E-25AXC	CY7C0241E-25AXC (pdf)

Related Parts	Information
CY7C0241E-15AXC	CY7C0241E-15AXC
CY7C0241E-15AXI	CY7C0241E-15AXI
CY7C0241E-15AXCT	CY7C0241E-15AXCT
CY7C0241E-25AXCT	CY7C0241E-25AXCT

PDF Datasheet Preview
CY7C024E, CY7C0241E CY7C025E, CY7C0251E 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY • True dual-ported memory cells that allow simultaneous reads of the same memory location • 4K x16 organization CY7C024E • 4K x 18 organization CY7C0241E • 8K x 16 organization CY7C025E • 8K x 18 organization CY7C0251E • complementary metal oxide semiconductor CMOS for optimum speed and power • High-speed access 15 ns • Low operating power ICC = 180 mA typ , ISB3 = mA typ • Fully asynchronous operation • Automatic power-down • Expandable data bus to 32/36 bits or more using master/slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flag for port-to-port communication • Separate upper-byte and lower-byte control • Pin select for master or slave • Available in Pb-free 100-pin thin quad flatpack TQFP package Selection Guide Parameter Maximum access time ns Typical operating current mA Typical standby current for ISB1 mA Functional Description The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are low-power CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024E/CY7C0241E and CY7C025E/CY7C0251E to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. CY7C024E/CY7C0241E CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit dual-port static RAMs or multiple devices can be combined to function as a 32-/36-bit or wider master/ slave dual-port static RAM. An M/S pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins Chip Enable CE , Read or Write Enable R/W , and Output Enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a CE pin. The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are available in 100-pin Pb-free TQFP. • San Jose, CA 95134-1709 • 408-943-2600 CY7C024E, CY7C0241E CY7C025E, CY7C0251E Logic Block Diagram L OE L R/WR UBR LBR CER [10] I/O 8L I/O 15L [9] 7L [6] BUSYL 12 Switching Waveforms 12 Ordering Information 4K x16 Dual-Port SRAM .......... 19 Ordering Information 8K x 16 Dual-Port SRAM ......... 19 Ordering Information 4K x 18 Dual-Port SRAM ......... 19 Ordering Information 8K x 18 Dual-Port SRAM 19 Ordering Code 19 Package Diagrams 21 Document History 22 Sales, Solutions, and Legal Information 22 Worldwide Sales and Design Support....................... 22 Products 22 PSoC Solutions 22 Page 3 of 22 Pin Configurations CY7C024E, CY7C0241E CY7C025E, CY7C0251E Figure 100-Pin TQFP Top View I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL LBL NC [4] A11L A10L A9L A8L A7L A6L I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CY7C024E/CY7C025E 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R R/WR GND SEMR CER UBR LBR NC[5] A11R A10R A9R A8R A7R A6R A5R Notes A12L on the CY7C025E/CY7C0251E. A12R on the CY7C025E/CY7C0251E. Page 4 of 22 CY7C024E, CY7C0241E CY7C025E, CY7C0251E Figure 100-Pin TQFP Top View 100-Pin TQFP Top View I/O10L I/O9L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL LBL NC[6] A11L A10L A9L A8L A7L A6L NC I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L GND I/O15L I/O16L VCC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CY7C0241/CY7C0251E 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC I/O7R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND I/O16R O ER R/WR GND SEMR CER UBR LBR NC[7] A11R A10R Ordering Information 4K x16 Dual-Port SRAM Speed ns 15 25 Ordering Code CY7C024E-15AXC CY7C024E-25AXC CY7C024E-25AXI CY7C024E-55AXC Package Name A100 Package Type 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP Ordering Information 8K x 16 Dual-Port SRAM Speed ns 25 Ordering Code CY7C025E-25AXC CY7C025E-25AXI CY7C025E-55AXC Package Name A100 A100 A100 Package Type 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP Ordering Information 4K x 18 Dual-Port SRAM Speed ns 15 Ordering Code CY7C0241E-15AXC CY7C0241E-15AXI CY7C0241E-25AXC Package Name A100 A100 A100 Package Type 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP Ordering Information 8K x 18 Dual-Port SRAM Speed ns Ordering Code Package Name A100 Package Type 100-Pin Pb-free TQFP Ordering Code Definition CY 7 C 02X 1 E Operating Range Commercial Industrial Commercial Operating Range Commercial Industrial Commercial Operating Range Commercial Industrial Commercial Operating Range Commercial 64 /128 KB Dual Port Family Technology CMOS Marketing Code 7 = SRAM Company ID CY=Cypress Page 19 of 22 CY7C024E, CY7C0241E CY7C025E, CY7C0251E Package Diagrams Figure 100-Pin Pb-free Thin Quad Flat Pack TQFP A100 Acronyms Acronym CMOS CE OE RAM TQFP Description Complementary metal oxide semiconductor Chip enable Output enable Random access memory Thin quad plastic flatpack 51-85048 D Page 20 of 22 CY7C024E, CY7C0241E CY7C025E, CY7C0251E Document History Page Document Title CY7C024E, CY7C0241E, CY7C025E, CY7C0251E, 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY Document Number 001-62932 ECN No. Orig. of Change Submission Date Description of Change * 2975554 RAME 07/09/2010 New Datasheet *A 3056347 ADMU 10/28/2010 Updated “Selection Guide” on page 1 For speed bin -25 Typical Operating current mA changed from 180 to 170, Typical standby current for ISB1 mA changed from 45 to 40 For speed bin -55 Typical Operating current mA changed from 180 to 150, Typical standby current for ISB1 mA changed from 45 to 20 Updated “Electrical Characteristics Over the Operating Range” on page 9 The values for the speed bins -25 and -55 have been put into separate columns. The values for Commercial parts have been modified for the following parameters no degradation of spec Operating Current ICC “180 typ / 275 max ” changed to “170 typ / 250 max for speed bin -25” and “150 typ / 230 max for speed bin -55” Standby Current ISB1 both ports TTL levels “45 typ / 65 max ” changed to “40 typ / 60 max for speed bin -25”, and “20 typ / 50 max for speed bin -55” Standby Current ISB2 one port TTL level “110 typ / 160 max ” changed to “100 typ / 150 max for speed bin -25”, and “75 typ / 135 max for speed bin -55” Standby Current ISB4 both ports CMOS Levels “100 typ / 140 max ” changed to “90 typ / 130 max for speed bin -25”, and “70 typ / 120 max for speed bin -55” Updated “Ordering Information 4K x 18 Dual-Port SRAM ” on page 19 Removed part CY7C0241E - 55AXI from ordering information. Page 21 of 22 CY7C024E, CY7C0241E CY7C025E, CY7C0251E Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All product and company names mentioned in this document are the trademarks of their respective holders. Page 22 of 22

PDF Datasheet Preview

CY7C024E, CY7C0241E CY7C025E, CY7C0251E
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
• True dual-ported memory cells that allow simultaneous reads of the same memory location
• 4K x16 organization CY7C024E
• 4K x 18 organization CY7C0241E
• 8K x 16 organization CY7C025E
• 8K x 18 organization CY7C0251E
• complementary metal oxide semiconductor CMOS for
optimum speed and power
• High-speed access 15 ns
• Low operating power ICC = 180 mA typ , ISB3 = mA typ
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using master/slave
chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for master or slave
• Available in Pb-free 100-pin thin quad flatpack TQFP package

Selection Guide

Parameter

Maximum access time ns

Typical operating current mA

Typical standby current for ISB1 mA

Functional Description

The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are
low-power CMOS 4K x 16/18 and 8K x 16/18 dual-port static

RAMs. Various arbitration schemes are included on the

CY7C024E/CY7C0241E and CY7C025E/CY7C0251E to handle
situations when multiple processors access the same piece of
data. Two ports are provided, permitting independent,
asynchronous access for reads and writes to any location in
memory.

CY7C024E/CY7C0241E

CY7C025E/CY7C0251E can be used as standalone 16 or 18-bit
dual-port static RAMs or multiple devices can be combined to
function as a 32-/36-bit or wider master/ slave dual-port static

RAM. An M/S pin is provided for implementing 32-/36-bit or wider
memory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.

Each port has independent control pins Chip Enable CE , Read or Write Enable R/W , and Output Enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a CE pin.

The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are available in 100-pin Pb-free TQFP.
• San Jose, CA 95134-1709
• 408-943-2600

CY7C024E, CY7C0241E CY7C025E, CY7C0251E

Logic Block Diagram

L OE L

R/WR UBR

LBR CER
[10] I/O 8L I/O 15L
[9] 7L
[6] BUSYL
12 Switching Waveforms 12 Ordering Information 4K x16 Dual-Port SRAM .......... 19 Ordering Information 8K x 16 Dual-Port SRAM ......... 19 Ordering Information 4K x 18 Dual-Port SRAM ......... 19 Ordering Information 8K x 18 Dual-Port SRAM 19
Ordering Code 19 Package Diagrams 21 Document History 22 Sales, Solutions, and Legal Information 22

Worldwide Sales and Design Support....................... 22 Products 22 PSoC Solutions 22

Page 3 of 22

Pin Configurations

CY7C024E, CY7C0241E CY7C025E, CY7C0251E

Figure 100-Pin TQFP Top View

I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL LBL

NC [4]

A11L A10L A9L A8L A7L A6L

I/O10L I/O11L I/O12L I/O13L GND

I/O14L I/O15L

VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

CY7C024E/CY7C025E
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S

BUSYR INTR A0R A1R A2R A3R A4R NC

I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O15R

R/WR GND SEMR

CER UBR LBR

NC[5]

A11R A10R A9R A8R A7R A6R A5R

Notes A12L on the CY7C025E/CY7C0251E. A12R on the CY7C025E/CY7C0251E.

Page 4 of 22

CY7C024E, CY7C0241E CY7C025E, CY7C0251E

Figure 100-Pin TQFP Top View
100-Pin TQFP Top View

I/O10L I/O9L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL SEML CEL UBL LBL NC[6] A11L A10L A9L A8L A7L A6L

NC I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L GND

I/O15L I/O16L

VCC GND

I/O0R I/O1R I/O2R

I/O3R

I/O4R I/O5R I/O6R I/O8R I/O17R
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

CY7C0241/CY7C0251E
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S

BUSYR INTR A0R A1R A2R A3R A4R NC

I/O7R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND I/O16R O ER R/WR GND SEMR CER UBR

LBR NC[7] A11R A10R
Ordering Information 4K x16 Dual-Port SRAM

Speed ns 15 25
Ordering Code

CY7C024E-15AXC CY7C024E-25AXC CY7C024E-25AXI CY7C024E-55AXC

Package Name A100

Package Type
100-Pin Pb-free TQFP 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP
Ordering Information 8K x 16 Dual-Port SRAM

Speed ns 25
Ordering Code

CY7C025E-25AXC CY7C025E-25AXI CY7C025E-55AXC

Package Name

A100

A100

A100

Package Type
100-Pin Pb-free TQFP 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP
Ordering Information 4K x 18 Dual-Port SRAM

Speed ns 15
Ordering Code

CY7C0241E-15AXC CY7C0241E-15AXI CY7C0241E-25AXC

Package Name

A100

A100

A100

Package Type
100-Pin Pb-free TQFP 100-Pin Pb-free TQFP 100-Pin Pb-free TQFP
Ordering Information 8K x 18 Dual-Port SRAM

Speed ns
Ordering Code

Package Name

A100

Package Type 100-Pin Pb-free TQFP
Ordering Code Definition

CY 7 C 02X 1 E

Operating Range

Commercial

Industrial Commercial

Operating Range

Commercial Industrial

Commercial

Operating Range

Commercial Industrial

Commercial

Operating Range

Commercial
64 /128 KB Dual Port Family Technology CMOS Marketing Code 7 = SRAM Company ID CY=Cypress

Page 19 of 22

CY7C024E, CY7C0241E CY7C025E, CY7C0251E

Package Diagrams

Figure 100-Pin Pb-free Thin Quad Flat Pack TQFP A100

Acronyms

Acronym CMOS CE OE RAM TQFP

Description Complementary metal oxide semiconductor Chip enable Output enable Random access memory Thin quad plastic flatpack
51-85048 *D

Page 20 of 22

CY7C024E, CY7C0241E CY7C025E, CY7C0251E

Document History Page

Document Title CY7C024E, CY7C0241E, CY7C025E, CY7C0251E, 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY Document Number 001-62932

ECN No.

Orig. of Change

Submission Date

Description of Change
** 2975554 RAME 07/09/2010 New Datasheet
*A 3056347 ADMU 10/28/2010 Updated “Selection Guide” on page 1 For speed bin -25 Typical Operating current mA changed from 180 to 170, Typical standby current for ISB1 mA changed from 45 to 40 For speed bin -55 Typical Operating current mA changed from 180 to 150, Typical standby current for ISB1 mA changed from 45 to 20

Updated “Electrical Characteristics Over the Operating Range” on page 9 The values for the speed bins -25 and -55 have been put into separate columns. The values for Commercial parts have been modified for the following parameters no degradation of spec Operating Current ICC “180 typ / 275 max ” changed to “170 typ / 250 max for speed bin -25” and “150 typ / 230 max for speed bin -55” Standby Current ISB1 both ports TTL levels “45 typ / 65 max ” changed to “40 typ / 60 max for speed bin -25”, and “20 typ / 50 max for speed bin -55” Standby Current ISB2 one port TTL level “110 typ / 160 max ” changed to “100 typ / 150 max for speed bin -25”, and “75 typ / 135 max for speed bin -55” Standby Current ISB4 both ports CMOS Levels “100 typ / 140 max ” changed to “90 typ / 130 max for speed bin -25”, and “70 typ / 120 max for speed bin -55”
Updated “Ordering Information 4K x 18 Dual-Port SRAM ” on page 19 Removed part CY7C0241E - 55AXI from ordering information.

Page 21 of 22

CY7C024E, CY7C0241E CY7C025E, CY7C0251E

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All product and company names mentioned in this document are the trademarks of their respective holders.

Page 22 of 22

More datasheets: H-300-1-500 | H-300-1-580 | H-300-2-500 | H-300-1-560 | H-300-2-520 | H-300-2-540 | H-300-2-580 | H-300-2-560 | U90-B305-4081-100 | CY7C0241E-15AXC

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C0241E-25AXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C0241E-25AXC 507849