CY7C009-15AC

CY7C009-15AC Datasheet

CY7C008/009 CY7C018/019

Part	Datasheet
CY7C009-15AC	CY7C009-15AC (pdf)

Related Parts	Information
CY7C018-15AC	CY7C018-15AC
CY7C019-15AC	CY7C019-15AC
CY7C009-15AXC	CY7C009-15AXC

PDF Datasheet Preview
25/0251 CY7C008/009 CY7C018/019 • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 64K x 8 organization CY7C008 • 128K x 8 organization CY7C009 • 64K x 9 organization CY7C018 • 128K x 9 organization CY7C019 • 0.35-micron CMOS for optimum speed/power • High-speed access 12[1]/15/20 ns • Low operating power Active ICC = 180 mA typical Standby ISB3 = mA typical Logic Block Diagram R/WL CE0L CE1L 64K/128K x 8/9 Dual-Port Static RAM • Fully asynchronous operation • Automatic power-down • Expandable data bus to 16/18 bits or more using Mas- ter/Slave chip select when using more than one device • On-chip arbitration logic • Semaphores included to permit software handshaking between ports • INT flags for port-to-port communication • Dual Chip Enables • Pin select for Master or Slave • Commercial and Industrial temperature ranges • Available in 100-pin TQFP • Pin-compatible and functionally equivalent to IDT7008 R/WR CE0R CE1R I/O Control I/O Control 16/17 Address Decode True Dual-Ported RAM Array R/WL SEML BUSYL INTL 16/17 Interrupt Semaphore Arbitration See page 6 for Load Conditions. for x8 devices for x9 devices. for 64K devices for 128K. BUSY is an output in master mode and an input in slave mode. Address Decode 16/17 16/17 CER OER R/WR SEMR BUSYR INTR Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 CY7C008/009 CY7C018/019 Functional Description The CY7C008/009 and CY7C018/019 are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select CE pin. The CY7C008/009 and CY7C018/019 are available in 100-pin Thin Quad Plastic Flatpack TQFP packages. Pin Configurations 100-Pin TQFP Top View NC A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L [5] A16L VCC NC CE0L CE1L SEML R/WL OEL GND NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CY7C009 128K x 8 Ordering Information 64K x8 Asynchronous Dual-Port SRAM Speed ns 12[1] Ordering Code CY7C008-12AC CY7C008-15AC CY7C008-20AC Package Name A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 128K x 8 Asynchronous Dual-Port SRAM Speed ns 12[1] Ordering Code CY7C009-12AC CY7C009-15AC CY7C009-20AC CY7C009-20AI Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 64K x 9 Asynchronous Dual-Port SRAM Speed ns 12[1] Ordering Code CY7C018-12AC CY7C018-15AC CY7C018-20AC Package Name A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 128K x 9 Asynchronous Dual-Port SRAM Speed ns 12[1] Ordering Code CY7C019-12AC CY7C019-15AC CY7C019-20AC CY7C019-20AI Package Name A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack CY7C008/009 CY7C018/019 Operating Range Commercial Operating Range Commercial Industrial Operating Range Commercial Operating Range Commercial Industrial Page 17 of 19 Package Diagram 100-Pin Thin Plastic Quad Flat Pack TQFP A100 CY7C008/009 CY7C018/019 51-85048-B Page 18 of 19 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C008/009 CY7C018/019 Document Title CY7C008/009, CY7C018/019 64K/128K x 8/9 Dual Port Static RAM Document Number 38-06041 Issue ECN NO. Date Orig. of Change Description of Change 110189 09/29/01 SZV Change from Spec number 38-00665 to 38-06041 113542 04/15/02 OOR Change pin 85 from BUSYL to BUSYR pg. 3 Page 19 of 19

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25/0251

CY7C008/009 CY7C018/019
• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 64K x 8 organization CY7C008
• 128K x 8 organization CY7C009
• 64K x 9 organization CY7C018
• 128K x 9 organization CY7C019
• 0.35-micron CMOS for optimum speed/power
• High-speed access 12[1]/15/20 ns
• Low operating power

Active ICC = 180 mA typical Standby ISB3 = mA typical

Logic Block Diagram

R/WL

CE0L CE1L
64K/128K x 8/9 Dual-Port Static RAM
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to IDT7008

R/WR CE0R CE1R

I/O Control

I/O Control
16/17

Address Decode

True Dual-Ported RAM Array

R/WL SEML

BUSYL INTL
16/17

Interrupt Semaphore Arbitration

See page 6 for Load Conditions. for x8 devices for x9 devices. for 64K devices for 128K. BUSY is an output in master mode and an input in slave mode.

Address Decode
16/17
16/17

CER OER

R/WR SEMR

BUSYR INTR

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose
• CA 95134
• 408-943-2600

CY7C008/009 CY7C018/019

Functional Description

The CY7C008/009 and CY7C018/019 are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Each port has independent control pins chip enable CE , read or write enable R/W , and output enable OE . Two flags are provided on each port BUSY and INT . BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag INT permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch semaphore at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select CE pin.

The CY7C008/009 and CY7C018/019 are available in 100-pin Thin Quad Plastic Flatpack TQFP packages.

Pin Configurations
100-Pin TQFP Top View

NC A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R NC

NC A7L A8L A9L A10L A11L A12L A13L A14L A15L [5] A16L VCC NC CE0L CE1L SEML R/WL OEL GND NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

CY7C009 128K x 8
Ordering Information
64K x8 Asynchronous Dual-Port SRAM

Speed ns 12[1]
Ordering Code CY7C008-12AC CY7C008-15AC CY7C008-20AC

Package Name

A100

A100

A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
128K x 8 Asynchronous Dual-Port SRAM

Speed ns 12[1]
Ordering Code CY7C009-12AC CY7C009-15AC CY7C009-20AC CY7C009-20AI

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
64K x 9 Asynchronous Dual-Port SRAM

Speed ns 12[1]
Ordering Code CY7C018-12AC CY7C018-15AC CY7C018-20AC

Package Name

A100

A100

A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack
128K x 9 Asynchronous Dual-Port SRAM

Speed ns 12[1]
Ordering Code CY7C019-12AC CY7C019-15AC CY7C019-20AC CY7C019-20AI

Package Name A100

Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack

CY7C008/009 CY7C018/019

Operating Range

Commercial

Operating Range

Commercial Industrial

Operating Range

Commercial

Operating Range

Commercial Industrial

Page 17 of 19

Package Diagram
100-Pin Thin Plastic Quad Flat Pack TQFP A100

CY7C008/009 CY7C018/019
51-85048-B

Page 18 of 19

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C008/009 CY7C018/019

Document Title CY7C008/009, CY7C018/019 64K/128K x 8/9 Dual Port Static RAM Document Number 38-06041

Issue ECN NO. Date

Orig. of Change Description of Change
110189 09/29/01 SZV

Change from Spec number 38-00665 to 38-06041
113542 04/15/02 OOR

Change pin 85 from BUSYL to BUSYR pg. 3

Page 19 of 19

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Datasheet ID: CY7C009-15AC 507846