CY7B991V-5JIT

CY7B991V-5JIT Datasheet

CY7B991V

Part	Datasheet
CY7B991V-5JIT	CY7B991V-5JIT (pdf)

Related Parts	Information
CY7B991V-2JCT	CY7B991V-2JCT

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CY7B991V V Low Voltage Programmable Skew Clock Buffer V Low Voltage Programmable Skew Clock Buffer • All output pair skew <100 ps typical 250 ps max • MHz to 80 MHz output operation • User-selectable output functions Selectable skew up to 18 ns Inverted and non-inverted Operation at one-half and one-quarter input frequency Operation at 2 x and 4 x input frequency input as low as MHz • Zero input to output delay • 50% duty cycle outputs • Low-voltage transistor-transistor logic LVTTL outputs drive 50 terminated lines • Operates from a single V supply • Low operating current • 32-pin plastic leaded chip carrier PLCC package • Low cycle-to-cycle jitter 100 ps typical Functional Description The CY7B991V V low-voltage programmable skew clock buffer LVPSCB offers user-selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Each of the eight individual drivers arranged in four pairs of user controllable outputs can drive terminated transmission lines with impedances as low as 50 This delivers minimal output skews and full-swing logic levels LVTTL . Each output is hardwired to one of nine delay or function configurations. Delay increments of to ns are determined by the operating frequency, with outputs able to skew up to ±6 time units from their nominal ‘zero’ skew position. The completely-integrated phase-locked loop PLL allows external load and transmission line delay effects to be canceled. When this ‘zero delay’ capability of the LVPSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that is multiplied by two or four at the clock destination. This feature minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility. For a complete list of related resources, click here. Logic Block Diagram TEST FB REF PHASE FREQ FILTER DET VCO AND TIME UNIT GENERATOR SELECT INPUTS THREE LEVEL 3F0 SKEW 3F1 3Q1 SELECT 2Q0 2F0 MATRIX 1F1 1Q1 • San Jose, CA 95134-1709 • 408-943-2600 CY7B991V Contents Pinouts 3 Pin Definitions 3 Block Diagram Description 4 Phase Frequency Detector and Filter 4 VCO and Time Unit Generator 4 Skew Select Matrix 4 Test Mode 5 Operational Mode Descriptions 6 Maximum Ratings 9 Operating Range 9 Electrical Characteristics 9 Capacitance 10 Thermal Resistance 10 AC Test Loads and Waveforms 10 Switching Characteristics -2 option 11 Switching Characteristics -5 Option 12 Switching Characteristics -7 Option 13 AC Timing Diagrams 14 Ordering Information 15 Package Diagram 16 Acronyms 17 Document Conventions 17 Units of Measure 17 Document History Page 18 Sales, Solutions, and Legal Information 20 Worldwide Sales and Design Support 20 Products 20 Cypress Developer Community 20 Technical Support 20 Page 2 of 20 Pinouts Figure 32-pin PLCC pinout 3F0 FS VCCQ REF GND TEST 2F1 3F1 4F0 4F1 VCCQ VCCN 4Q1 4Q0 GND 4 3 2 1 32 31 30 14 15 16 17 18 19 20 2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND CY7B991V 3Q1 3Q0 VCCN 2Q1 2Q0 Pin Definitions Pin Name Pin Number FB FS 1F0, 1F1 2F0, 2F1 3F0, 3F1 4F0, 4F1 TEST 1Q0, 1Q1 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1 VCCN VCCQ GND 17 3 26, 27 29, 30 4, 5 6, 7 31 24, 23 20, 19 15, 14 11, 10 9, 16, 18, 25 2, 8 12, 13, 21, 22, 28, 32 I/O I I O PWR Description Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. PLL feedback input typically connected to one of the eight outputs . Three-level frequency range select. See Table Three-level function select inputs for output pair 1 1Q0, 1Q1 . See Table Three-level function select inputs for output pair 2 2Q0, 2Q1 . See Table Three-level function select inputs for output pair 3 3Q0, 3Q1 . See Table Three-level function select inputs for output pair 4 4Q0, 4Q1 . See Table Three-level select. See test mode section under the block diagram descriptions. Output pair See Table Output pair See Table Output pair See Table Output pair See Table Power supply for output drivers. Power supply for internal circuitry. Ground. Page 3 of 20 CY7B991V Block Diagram Description Phase Frequency Detector and Filter The phase frequency detector and filter blocks accept inputs from the reference frequency REF input and the feedback FB input. They generate correction information to control the frequency of the voltage controlled oscillator VCO . These blocks, along with the VCO, form a PLL that tracks the incoming REF signal. VCO and Time Unit Generator The VCO accepts analog control inputs from the PLL filter block. It generates a frequency that is used by the time unit generator to create discrete time units, selected in the skew select matrix. The operational range of the VCO is determined by the FS control pin. The time unit tU is determined by the operating frequency of the device and the level of the FS pin as shown in Table Table Frequency Range Select and tU Calculation[1] FS[2, 3] fNOM MHz Min Max -----------1-----------fNOM N where N = Approximate Frequency MHz At Which tU = ns LOW 15 30 25 50 HIGH 40 80 Skew Select Matrix The skew select matrix is comprised of four independent sections. Each section has two low-skew, high fanout drivers xQ0, xQ1 , and two corresponding three-level function select xF0, xF1 inputs. Table 2 shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected. Table Programmable Skew Configurations [1] Ordering Information Speed ps Ordering Code 250 500 Pb-free 250 500 CY7B991V-2JC CY7B991V-2JCT CY7B991V-5JI CY7B991V-5JIT CY7B991V-2JXC CY7B991V-2JXCT CY7B991V-5JXC CY7B991V-5JXCT CY7B991V-5JXI CY7B991V-5JXIT CY7B991V-7JXC CY7B991V-7JXCT Package Type 32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel Operating Range Commercial Industrial Commercial Industrial Commercial Ordering Code Definitions CY 7B991V - X J X X = blank or T blank = Tube T = Tape and Reel Temperature Range X = C or I C = Commercial = 0 C to +70 C I = Industrial = C to 85 C X = Pb-free X Absent = Leaded Package Type J = 32-pin PLCC Device Option Performance X = 2 or 5 or 7 Base Part Number Company ID CY = Cypress Page 15 of 20 CY7B991V Package Diagram Figure 32-pin PLCC x Inches J32 Package Outline, 51-85002 51-85002 *E Page 16 of 20 CY7B991V Acronyms Table Acronyms Used in this Document Acronym CMOS Complementary Metal Oxide Semiconductor Feedback LVPSCB Low-Voltage Programmable Skew Clock Buffer LVTTL Low-Voltage Transistor-Transistor Logic Phase-Locked Loop PLCC Plastic Leaded Chip Carrier Reference Frequency Root Mean Square Voltage Controlled Oscillator Document Conventions Units of Measure Table Units of Measure Symbol °C µA µs mA ms mW MHz Unit of Measure degree Celsius kilohm microampere microsecond milliampere millisecond milliwatt megahertz nanosecond picofarad picosecond volt watt Page 17 of 20 CY7B991V Added typical value of tJR parameter as “100 ps” corresponding to “Peak”. Updated Ordering Information: Updated part numbers. 1199925 See ECN KVM / Removed “Switching Characteristics -2 option ”. AESA Updated Ordering Information: No change in part numbers. Changed format only. 1286064 See ECN AESA Change status from Preliminary to Final. 2584293 10/10/08 AESA Added Switching Characteristics -2 option . Updated to new template. 2761988 09/10/09 CXQ Updated Test Mode: Replaced “100W resistor” with resistor”. Updated Ordering Information: No change in part numbers. Replaced “Pb” with “pin” in “Package Type” column. 2905834 04/06/2010 CXQ Updated Ordering Information: Removed inactive part numbers CY7B991V-5JC, CY7B991V-5JCT, CY7B991V-7JC and CY7B991V-7JCT. Updated Package Diagram. 3041840 09/29/2010 CXQ Fixed various format and typographical errors. Updated Pinouts: Updated Figure 1 Fixed pin 8 label . Updated Pin Definitions: Added “Pin Number” column. Updated Electrical Characteristics: Removed values from “Max” column of ILL and IOS parameters and added the same values in “Min” column. Removed note “These inputs are normally wired to VCC, GND, or left unconnected actual threshold voltages vary as a percentage of VCC . Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved.” and its reference in “Description” column of PD parameter. 4161003 10/16/2013 CINM Updated Package Diagram: Updated to new template. 4598452 12/16/2014 TAVA Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Added AC Timing Diagrams. Page 18 of 20 CY7B991V Document History Page continued Document Title CY7B991V, V Low Voltage Programmable Skew Clock Buffer Document Number 38-07141 Submission Orig. of Change Description of Change 4644120 01/28/2015 TAVA Updated Switching Characteristics -2 option : Updated description of tRPWH and tRPWL parameters. Changed minimum value of tRPWH parameter from 5 ns to ns. Changed minimum value of tRPWL parameter from 5 ns to ns. Updated Switching Characteristics -5 Option : Updated description of tRPWH and tRPWL parameters. Changed minimum value of tRPWH parameter from 5 ns to ns. Changed minimum value of tRPWL parameter from 5 ns to ns. Updated Switching Characteristics -7 Option : Updated description of tRPWH and tRPWL parameters. Changed minimum value of tRPWH parameter from 5 ns to ns. Changed minimum value of tRPWL parameter from 5 ns to ns. Updated Package Diagram: 5276098 05/18/2016 PSR Updated Electrical Characteristics: Updated Note 8 Replaced “FC = F < C” with “FC = F x C” . Added Thermal Resistance. Updated to new template. 5507104 11/02/2016 PAWK Updated Sales, Solutions, and Legal Information and added WICED in the copyright notice. Page 19 of 20 CY7B991V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Microcontrollers

PDF Datasheet Preview

CY7B991V

V Low Voltage Programmable Skew Clock Buffer

V Low Voltage Programmable Skew Clock Buffer
• All output pair skew <100 ps typical 250 ps max
• MHz to 80 MHz output operation
• User-selectable output functions Selectable skew up to 18 ns Inverted and non-inverted Operation at one-half and one-quarter input frequency Operation at 2 x and 4 x input frequency input as low as MHz
• Zero input to output delay
• 50% duty cycle outputs
• Low-voltage transistor-transistor logic LVTTL outputs drive 50 terminated lines
• Operates from a single V supply
• Low operating current
• 32-pin plastic leaded chip carrier PLCC package
• Low cycle-to-cycle jitter 100 ps typical

Functional Description

The CY7B991V V low-voltage programmable skew clock buffer LVPSCB offers user-selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Each of the eight individual drivers arranged in four pairs of user controllable outputs can drive terminated transmission lines with impedances as low as 50 This delivers minimal output skews and full-swing logic levels LVTTL .

Each output is hardwired to one of nine delay or function configurations. Delay increments of to ns are determined by the operating frequency, with outputs able to skew up to ±6 time units from their nominal ‘zero’ skew position. The completely-integrated phase-locked loop PLL allows external load and transmission line delay effects to be canceled. When this ‘zero delay’ capability of the LVPSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that is multiplied by two or four at the clock destination. This feature minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility.

For a complete list of related resources, click here.

Logic Block Diagram

TEST

FB REF

PHASE

FREQ FILTER DET

VCO AND TIME UNIT GENERATOR

SELECT

INPUTS

THREE

LEVEL 3F0

SKEW
3F1 3Q1

SELECT
2Q0 2F0

MATRIX
1F1 1Q1
• San Jose, CA 95134-1709
• 408-943-2600

CY7B991V

Contents

Pinouts 3 Pin Definitions 3 Block Diagram Description 4

Phase Frequency Detector and Filter 4 VCO and Time Unit Generator 4 Skew Select Matrix 4 Test Mode 5 Operational Mode Descriptions 6 Maximum Ratings 9 Operating Range 9 Electrical Characteristics 9 Capacitance 10 Thermal Resistance 10 AC Test Loads and Waveforms 10 Switching Characteristics -2 option 11 Switching Characteristics -5 Option 12
Switching Characteristics -7 Option 13 AC Timing Diagrams 14 Ordering Information 15 Package Diagram 16 Acronyms 17 Document Conventions 17

Units of Measure 17 Document History Page 18 Sales, Solutions, and Legal Information 20

Worldwide Sales and Design Support 20 Products 20 Cypress Developer Community 20 Technical Support 20

Page 2 of 20

Pinouts

Figure 32-pin PLCC pinout
3F0 FS VCCQ REF GND TEST 2F1
3F1 4F0 4F1 VCCQ VCCN 4Q1 4Q0 GND
4 3 2 1 32 31 30
14 15 16 17 18 19 20
2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND

CY7B991V
3Q1 3Q0 VCCN
2Q1 2Q0

Pin Definitions

Pin Name Pin Number

FB FS 1F0, 1F1 2F0, 2F1 3F0, 3F1 4F0, 4F1 TEST 1Q0, 1Q1 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1 VCCN VCCQ GND
17 3 26, 27 29, 30 4, 5 6, 7 31 24, 23 20, 19 15, 14 11, 10 9, 16, 18, 25 2, 8 12, 13, 21, 22, 28, 32

I/O I

I O PWR

Description Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. PLL feedback input typically connected to one of the eight outputs . Three-level frequency range select. See Table Three-level function select inputs for output pair 1 1Q0, 1Q1 . See Table Three-level function select inputs for output pair 2 2Q0, 2Q1 . See Table Three-level function select inputs for output pair 3 3Q0, 3Q1 . See Table Three-level function select inputs for output pair 4 4Q0, 4Q1 . See Table Three-level select. See test mode section under the block diagram descriptions. Output pair See Table Output pair See Table Output pair See Table Output pair See Table Power supply for output drivers. Power supply for internal circuitry. Ground.

Page 3 of 20

CY7B991V

Block Diagram Description

Phase Frequency Detector and Filter

The phase frequency detector and filter blocks accept inputs from the reference frequency REF input and the feedback FB input. They generate correction information to control the frequency of the voltage controlled oscillator VCO . These blocks, along with the VCO, form a PLL that tracks the incoming REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter block. It generates a frequency that is used by the time unit generator to create discrete time units, selected in the skew select matrix. The operational range of the VCO is determined by the FS control pin. The time unit tU is determined by the operating frequency of the device and the level of the FS pin as shown in Table

Table Frequency Range Select and tU Calculation[1]

FS[2, 3]
fNOM MHz Min Max
-----------1-----------fNOM N
where N =

Approximate Frequency MHz At

Which tU = ns

LOW 15 30
25 50

HIGH 40 80

Skew Select Matrix

The skew select matrix is comprised of four independent sections. Each section has two low-skew, high fanout drivers xQ0, xQ1 , and two corresponding three-level function select xF0, xF1 inputs. Table 2 shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected.

Table Programmable Skew Configurations [1]
Ordering Information

Speed ps
Ordering Code
250 500 Pb-free 250 500

CY7B991V-2JC CY7B991V-2JCT CY7B991V-5JI CY7B991V-5JIT

CY7B991V-2JXC CY7B991V-2JXCT CY7B991V-5JXC CY7B991V-5JXCT CY7B991V-5JXI CY7B991V-5JXIT CY7B991V-7JXC CY7B991V-7JXCT

Package Type
32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel
32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel 32-pin PLCC 32-pin PLCC Tape and Reel

Operating Range

Commercial Industrial

Commercial Industrial Commercial
Ordering Code Definitions CY 7B991V - X J X

X = blank or T blank = Tube T = Tape and Reel

Temperature Range X = C or I C = Commercial = 0 C to +70 C I = Industrial = C to 85 C

X = Pb-free X Absent = Leaded

Package Type J = 32-pin PLCC

Device Option Performance X = 2 or 5 or 7

Base Part Number

Company ID CY = Cypress

Page 15 of 20

CY7B991V

Package Diagram

Figure 32-pin PLCC x Inches J32 Package Outline, 51-85002
51-85002 *E

Page 16 of 20

CY7B991V

Acronyms

Table Acronyms Used in this Document

Acronym

CMOS Complementary Metal Oxide Semiconductor

Feedback

LVPSCB Low-Voltage Programmable Skew Clock Buffer

LVTTL

Low-Voltage Transistor-Transistor Logic

Phase-Locked Loop

PLCC

Plastic Leaded Chip Carrier

Reference Frequency

Root Mean Square

Voltage Controlled Oscillator

Document Conventions

Units of Measure

Table Units of Measure

Symbol °C µA µs mA ms mW MHz

Unit of Measure degree Celsius kilohm microampere microsecond milliampere millisecond milliwatt megahertz
nanosecond
picofarad
picosecond
volt
watt

Page 17 of 20

CY7B991V
Added typical value of tJR parameter as “100 ps” corresponding to “Peak”. Updated Ordering Information:

Updated part numbers.
1199925 See ECN

KVM / Removed “Switching Characteristics -2 option ”.
AESA Updated Ordering Information:

No change in part numbers.

Changed format only.
1286064 See ECN

AESA Change status from Preliminary to Final.
2584293 10/10/08

AESA Added Switching Characteristics -2 option .

Updated to new template.
2761988 09/10/09

CXQ Updated Test Mode:

Replaced “100W resistor” with resistor”.
Updated Ordering Information:

No change in part numbers.

Replaced “Pb” with “pin” in “Package Type” column.
2905834 04/06/2010 CXQ Updated Ordering Information:

Removed inactive part numbers CY7B991V-5JC, CY7B991V-5JCT,

CY7B991V-7JC and CY7B991V-7JCT.

Updated Package Diagram.
3041840 09/29/2010 CXQ Fixed various format and typographical errors.

Updated Pinouts:

Updated Figure 1 Fixed pin 8 label .

Updated Pin Definitions:

Added “Pin Number” column.

Updated Electrical Characteristics:

Removed values from “Max” column of ILL and IOS parameters and added the same values in “Min” column.

Removed note “These inputs are normally wired to VCC, GND, or left unconnected actual threshold voltages vary as a percentage of VCC . Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may
require an additional tLOCK time before all datasheet limits are achieved.” and its reference in “Description” column of PD parameter.
4161003 10/16/2013 CINM Updated Package Diagram:

Updated to new template.
4598452 12/16/2014 TAVA Updated Functional Description:

Added “For a complete list of related resources, click here.” at the end.

Added AC Timing Diagrams.

Page 18 of 20

CY7B991V

Document History Page continued

Document Title CY7B991V, V Low Voltage Programmable Skew Clock Buffer Document Number 38-07141

Submission Orig. of

Change

Description of Change
4644120 01/28/2015 TAVA Updated Switching Characteristics -2 option :

Updated description of tRPWH and tRPWL parameters. Changed minimum value of tRPWH parameter from 5 ns to ns. Changed minimum value of tRPWL parameter from 5 ns to ns. Updated Switching Characteristics -5 Option :

Updated description of tRPWH and tRPWL parameters. Changed minimum value of tRPWH parameter from 5 ns to ns. Changed minimum value of tRPWL parameter from 5 ns to ns. Updated Switching Characteristics -7 Option :

Updated description of tRPWH and tRPWL parameters. Changed minimum value of tRPWH parameter from 5 ns to ns. Changed minimum value of tRPWL parameter from 5 ns to ns. Updated Package Diagram:
5276098 05/18/2016 PSR Updated Electrical Characteristics:

Updated Note 8 Replaced “FC = F < C” with “FC = F x C” .

Added Thermal Resistance.

Updated to new template.
5507104 11/02/2016 PAWK Updated Sales, Solutions, and Legal Information and added WICED in the
copyright notice.

Page 19 of 20

CY7B991V

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Microcontrollers

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7B991V-5JIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7B991V-5JIT 507844