CY7B9910-5SC

CY7B9910-5SC Datasheet

CY7B9910 CY7B9920

Part	Datasheet
CY7B9910-5SC	CY7B9910-5SC (pdf)

Related Parts	Information
CY7B9910-7SC	CY7B9910-7SC
CY7B9910-2SC	CY7B9910-2SC
CY7B9920-5SC	CY7B9920-5SC
CY7B9910-5SI	CY7B9910-5SI
CY7B9920-5SI	CY7B9920-5SI

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CY7B9910 CY7B9920 • All outputs skew <100 ps typical 250 max. • 15- to 80-MHz output operation • Zero input to output delay • 50% duty-cycle outputs • Outputs drive terminated lines • Low operating current • 24-pin SOIC package • Jitter <200 ps peak to peak, <25 ps RMS • Compatible with Pentium -based processors Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low-skew system clock distribution. These multiple-output clock drivers optimize the timing of high-performance computer systems. Eight individual drivers can each drive terminated transmission lines with impedances as low as while delivering minimal and specified output skews and full-swing logic levels CY7B9910 TTL or CY7B9920 CMOS . The completely integrated PLL allows “zero delay” capability. External divide capability, combined with the internal PLL, allows distribution of a low-frequency clock that can be multiplied by virtually any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. Logic Block Diagram Low Skew Clock Buffer Block Diagram Description Phase Frequency Detector and Filter These two blocks accept inputs from the reference frequency REF input and the feedback FB input and generate correction information to control the frequency of the Voltage-Controlled Oscillator VCO . These blocks, along with the VCO, form a Phase-Locked Loop PLL that tracks the incoming REF signal. The VCO accepts analog control inputs from the PLL filter block and generates a frequency. The operational range of the VCO is determined by the FS control pin. Test Mode The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910/CY7B9920 to operate as explained above. For testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a resistor. This will allow an external tester to change the state of these pins. If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase-locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. Pin Configuration TEST FB REF PHASE FREQ FILTER DET Voltage Controlled Oscillator FS Q0 Pentium is a trademark of Intel Corporation. VCCQ FS NC VCCQ VCCN Q1 GND Q2 Q3 VCCN SOIC Top View 6 7B9910 19 7 7B9920 18 GND TEST GND VCCN Q7 Q6 GND Q5 Q4 VCCN FB CY7B9910 CY7B9920 Pin Definitions Signal Name REF FB FS[9,10,11] TEST Q[0..7] VCCN VCCQ GND I/O I I O PWR Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. PLL feedback input typically connected to one of the eight outputs . Three-level frequency range select. Three-level select. See Test Mode section. Clock outputs. Power supply for output drivers. Power supply for internal circuitry. Ground. Maximum Ratings Above which the useful life may be impaired. For user guidelines, not tested. Storage Temperature to +150°C Ambient Temperature with Power to +125°C Supply Voltage to Ground Potential............... to +7.0V DC Input Voltage to +7.0V Output Current into Outputs LOW 64 mA Static Discharge Voltage >2001V per MIL-STD-883, Method 3015 Latch-Up >200 mA Ordering Information Accuracy ps 250 500 Ordering Code Document #: Package Diagram Package Name S13 Package Type 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead 300-Mil Molded SOIC S13 CY7B9910 CY7B9920 Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial

PDF Datasheet Preview

CY7B9910 CY7B9920
• All outputs skew <100 ps typical 250 max.
• 15- to 80-MHz output operation
• Zero input to output delay
• 50% duty-cycle outputs
• Outputs drive terminated lines
• Low operating current
• 24-pin SOIC package
• Jitter <200 ps peak to peak, <25 ps RMS
• Compatible with Pentium -based processors

Functional Description

The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low-skew system clock distribution. These multiple-output clock drivers optimize the timing of high-performance computer systems. Eight individual drivers can each drive terminated transmission lines with impedances as low as while delivering minimal and specified output skews and full-swing logic levels CY7B9910 TTL or CY7B9920 CMOS .

The completely integrated PLL allows “zero delay” capability. External divide capability, combined with the internal PLL, allows distribution of a low-frequency clock that can be multiplied by virtually any factor at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility.

Logic Block Diagram

Low Skew Clock Buffer

Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept inputs from the reference frequency REF input and the feedback FB input and generate correction information to control the frequency of the Voltage-Controlled Oscillator VCO . These blocks, along with the VCO, form a Phase-Locked Loop PLL that tracks the incoming REF signal.

The VCO accepts analog control inputs from the PLL filter block and generates a frequency. The operational range of the VCO is determined by the FS control pin.

Test Mode

The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the CY7B9910/CY7B9920 to operate as explained above. For testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a resistor. This will allow an external tester to change the state of these pins.

If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase-locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode.

Pin Configuration

TEST

FB REF

PHASE

FREQ FILTER DET

Voltage Controlled Oscillator

FS Q0

Pentium is a trademark of Intel Corporation.

VCCQ FS NC

VCCQ VCCN

Q1 GND

Q2 Q3 VCCN

SOIC Top View
6 7B9910 19 7 7B9920 18

GND TEST

GND VCCN Q7 Q6 GND Q5 Q4 VCCN FB

CY7B9910 CY7B9920

Pin Definitions

Signal Name REF

FB FS[9,10,11] TEST Q[0..7] VCCN VCCQ GND

I/O I

I O PWR

Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. PLL feedback input typically connected to one of the eight outputs . Three-level frequency range select. Three-level select. See Test Mode section. Clock outputs. Power supply for output drivers. Power supply for internal circuitry. Ground.

Maximum Ratings

Above which the useful life may be impaired. For user guidelines, not tested. Storage Temperature to +150°C Ambient Temperature with Power to +125°C Supply Voltage to Ground Potential............... to +7.0V DC Input Voltage to +7.0V Output Current into Outputs LOW 64 mA

Static Discharge Voltage >2001V per MIL-STD-883, Method 3015

Latch-Up >200 mA
Ordering Information

Accuracy ps 250 500
Ordering Code

Document #:

Package Diagram

Package Name S13

Package Type 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC 24-Lead Small Outline IC
24-Lead 300-Mil Molded SOIC S13

CY7B9910 CY7B9920

Operating Range

Commercial

Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial

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Datasheet ID: CY7B9910-5SC 507841