CY7B992-7JXCT

CY7B992-7JXCT Datasheet

CY7B991 CY7B992

Part	Datasheet
CY7B992-7JXCT	CY7B992-7JXCT (pdf)

Related Parts	Information
CY7B992-7JXC	CY7B992-7JXC
CY7B992-7JI	CY7B992-7JI

PDF Datasheet Preview
CY7B991 CY7B992 Programmable Skew Clock Buffer • All Output Pair Skew <100 ps Typical 250 ps maximum • MHz to 80 MHz Output Operation • User Selectable Output Functions Selectable Skew to 18 ns Inverted and Non-inverted Operation at and Input Frequency Operation at 2x and 4x Input Frequency input as low as MHz • Zero Input to Output Delay • 50% Duty Cycle Outputs • Outputs drive 50Ω terminated lines • Low Operating Current • 32-pin PLCC/LCC Package • Jitter <200 ps Peak-to-peak < 25 ps RMS Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers PSCB offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as They can deliver minimal and specified output skews and full swing logic levels CY7B991 TTL or CY7B992 CMOS . Each output is hardwired to one of the nine delay or function configurations. Delay increments of to ns are determined by the operating frequency with outputs that skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows cancellation of external load and transmission line delay effects. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, you can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that are multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility. Logic Block Diagram TEST FB REF PHASE FREQ FILTER DET VCO AND TIME UNIT GENERATOR SELECT INPUTS THREE LEVEL 3F0 SKEW 3F1 3Q1 SELECT 2Q0 2F0 MATRIX • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7B991 CY7B992 Contents Features Functional Description Logic Block Diagram Contents Pinouts Block Diagram Description Phase Frequency Detector and Filter VCO and Time Unit Generator Skew Select Matrix Test Mode Maximum Ratings Operating Range Electrical Characteristics Capacitance Switching Characteristics AC Timing Diagrams Operational Mode Descriptions Ordering Information Military Specifications Group A Subgroup Testing DC Characteristics Package Diagrams Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions Page 2 of 20 [+] Feedback Pinouts Figure Pin Configuration 32-Pin PLCC/LCC Package 3F0 FS VCCQ REF GND TEST 2F1 3F1 4F0 4F1 VCCQ VCCN 4Q1 4Q0 GND 4 3 2 1 32 31 30 CY7B991 CY7B992 14 15 16 17 18 19 20 2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND CY7B991 CY7B992 3Q1 3Q0 V 2Q1 2Q0 Table Pin Definition Signal Name FB FS 1F0, 1F1 2F0, 2F1 3F0, 3F1 4F0, 4F1 TEST 1Q0, 1Q1 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1 VCCN VCCQ GND I O PWR Description Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. PLL feedback input typically connected to one of the eight outputs . Three level frequency range select. See Table Three level function select inputs for output pair 1 1Q0, 1Q1 . See Table Three level function select inputs for output pair 2 2Q0, 2Q1 . See Table Three level function select inputs for output pair 3 3Q0, 3Q1 . See Table Three level function select inputs for output pair 4 4Q0, 4Q1 . See Table Three level select. See “Test Mode” on page 5 under the “Block Diagram Description” on page Output pair See Table Output pair See Table Output pair See Table Output pair See Table Power supply for output drivers. Power supply for internal circuitry. Ground. Page 3 of 20 [+] Feedback CY7B991 CY7B992 Block Diagram Description Phase Frequency Detector and Filter The Phase Frequency Detector and Filter blocks accept inputs from the reference frequency REF input and the feedback FB input and generate correction information to control the frequency of the Voltage Controlled Oscillator VCO . These blocks, along with the VCO, form a Phase Locked Loop PLL that tracks the incoming REF signal. VCO and Time Unit Generator The VCO accepts analog control inputs from the PLL filter block. It generates a frequency used by the time unit generator to create discrete time units that are selected in the skew select matrix. The operational range of the VCO is determined by the FS control pin. The time unit tU is determined by the operating frequency of the device and the level of the FS pin as shown in Table Table Frequency Range Select and tU Calculation[1] FS[2, 3] fNOM MHz Min Max -----------1-----------fNOM x N where N = Approximate Frequency MHz At Which tU = ns LOW 15 30 25 50 HIGH 40 80 Skew Select Matrix The skew select matrix contains four independent sections. Each section has two low skew, high fanout drivers xQ0, xQ1 , and two corresponding three level function select xF0, xF1 inputs. Table 3 shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected. Table Programmable Skew Configurations[1] Ordering Information Accuracy ps 250 Ordering Code Pb-Free 250 500 Package Type 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Page 17 of 20 [+] Feedback Military Specifications Group A Subgroup Testing DC Characteristics Parameter VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL ICCQ ICCN Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 CY7B991 CY7B992 Page 18 of 20 [+] Feedback Package Diagrams continued Figure 32-Pin Plastic Leaded Chip Carrier CY7B991 CY7B992 51-85002 *C Page 19 of 20 [+] Feedback CY7B991 CY7B992 Document History Page Document Title CY7B991/CY7B992 Programmable Skew Clock Buffer Document Number 38-07138 Orig. of Submission Change Description of Change 110247 12/19/01 Change from Specification number 38-00513 to 38-07138 1199925 KVM/AESA See ECN Add Pb-free part numbers. Update package names in Ordering Information table. Remove Pentium reference on page 1286064 AESA See ECN Change status to final 2750166 TSAI 08/10/09 Post to external web 2761988 CXQ 09/10/09 Fixed Ordering Infomation table replacement error of “lead” with “Pb”. 2894960 KVM 03/18/10 Removed following obsolete parts from the ordering information table CY7B991-7LMB, CY7B992-7LMB, CY7B992-5JI, CY7B992-5JIT Updated package diagram Updated sales links Added Table of Contents Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All trademarks or registered trademarks referenced herein are property of the respective corporations. Page 20 of 20 [+] Feedback

PDF Datasheet Preview

CY7B991 CY7B992

Programmable Skew Clock Buffer
• All Output Pair Skew <100 ps Typical 250 ps maximum
• MHz to 80 MHz Output Operation
• User Selectable Output Functions Selectable Skew to 18 ns Inverted and Non-inverted Operation at and Input Frequency Operation at 2x and 4x Input Frequency input as low as MHz
• Zero Input to Output Delay
• 50% Duty Cycle Outputs
• Outputs drive 50Ω terminated lines
• Low Operating Current
• 32-pin PLCC/LCC Package
• Jitter <200 ps Peak-to-peak < 25 ps RMS

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buffers PSCB offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as They can deliver minimal and specified output skews and full swing logic levels CY7B991 TTL or CY7B992 CMOS .

Each output is hardwired to one of the nine delay or function configurations. Delay increments of to ns are determined by the operating frequency with outputs that skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows cancellation of external load and transmission line delay effects. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, you can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that are multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility.

Logic Block Diagram TEST

FB REF

PHASE

FREQ FILTER DET

VCO AND TIME UNIT GENERATOR

SELECT

INPUTS

THREE

LEVEL 3F0

SKEW
3F1 3Q1

SELECT
2Q0 2F0

MATRIX
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7B991 CY7B992

Contents

Features Functional Description Logic Block Diagram Contents Pinouts Block Diagram Description

Phase Frequency Detector and Filter VCO and Time Unit Generator Skew Select Matrix Test Mode Maximum Ratings Operating Range Electrical Characteristics Capacitance
Switching Characteristics AC Timing Diagrams Operational Mode Descriptions Ordering Information Military Specifications

Group A Subgroup Testing DC Characteristics Package Diagrams Document History Page Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Products PSoC Solutions

Page 2 of 20 [+] Feedback

Pinouts

Figure Pin Configuration 32-Pin PLCC/LCC Package
3F0 FS VCCQ REF GND TEST 2F1
3F1 4F0 4F1 VCCQ VCCN 4Q1 4Q0 GND
4 3 2 1 32 31 30

CY7B991

CY7B992
14 15 16 17 18 19 20
2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND

CY7B991 CY7B992
3Q1 3Q0 V
2Q1 2Q0

Table Pin Definition

Signal Name

FB FS 1F0, 1F1 2F0, 2F1 3F0, 3F1 4F0, 4F1 TEST 1Q0, 1Q1 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1 VCCN VCCQ GND

I O PWR

Description Reference frequency input. This input supplies the frequency and timing against which all functional variations are measured. PLL feedback input typically connected to one of the eight outputs . Three level frequency range select. See Table Three level function select inputs for output pair 1 1Q0, 1Q1 . See Table Three level function select inputs for output pair 2 2Q0, 2Q1 . See Table Three level function select inputs for output pair 3 3Q0, 3Q1 . See Table Three level function select inputs for output pair 4 4Q0, 4Q1 . See Table Three level select. See “Test Mode” on page 5 under the “Block Diagram Description” on page Output pair See Table Output pair See Table Output pair See Table Output pair See Table Power supply for output drivers. Power supply for internal circuitry. Ground.

Page 3 of 20 [+] Feedback

CY7B991 CY7B992

Block Diagram Description

Phase Frequency Detector and Filter

The Phase Frequency Detector and Filter blocks accept inputs from the reference frequency REF input and the feedback FB input and generate correction information to control the frequency of the Voltage Controlled Oscillator VCO . These blocks, along with the VCO, form a Phase Locked Loop PLL that tracks the incoming REF signal.

VCO and Time Unit Generator

The VCO accepts analog control inputs from the PLL filter block. It generates a frequency used by the time unit generator to create discrete time units that are selected in the skew select matrix. The operational range of the VCO is determined by the FS control pin. The time unit tU is determined by the operating frequency of the device and the level of the FS pin as shown in Table

Table Frequency Range Select and tU Calculation[1]

FS[2, 3]
fNOM MHz Min Max
-----------1-----------fNOM x N
where N =

Approximate Frequency MHz At

Which tU = ns

LOW 15 30
25 50

HIGH 40 80

Skew Select Matrix

The skew select matrix contains four independent sections. Each section has two low skew, high fanout drivers xQ0, xQ1 , and two corresponding three level function select xF0, xF1 inputs. Table 3 shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected.

Table Programmable Skew Configurations[1]
Ordering Information

Accuracy ps 250
Ordering Code

Pb-Free 250 500

Package Type
32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel 32-Pin Plastic Leaded Chip Carrier 32-Pin Plastic Leaded Chip Carrier - Tape and Reel

Operating Range

Commercial Industrial Commercial Industrial Commercial Industrial

Commercial Industrial Commercial Industrial

Page 17 of 20 [+] Feedback

Military Specifications

Group A Subgroup Testing

DC Characteristics

Parameter

VOH VOL VIH VIL VIHH VIMM VILL IIH IIL IIHH IIMM IILL ICCQ ICCN

Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3

CY7B991 CY7B992

Page 18 of 20 [+] Feedback

Package Diagrams continued

Figure 32-Pin Plastic Leaded Chip Carrier

CY7B991 CY7B992
51-85002 *C

Page 19 of 20 [+] Feedback

CY7B991 CY7B992

Document History Page

Document Title CY7B991/CY7B992 Programmable Skew Clock Buffer Document Number 38-07138

Orig. of Submission

Change

Description of Change
110247
12/19/01 Change from Specification number 38-00513 to 38-07138
1199925 KVM/AESA See ECN Add Pb-free part numbers. Update package names in Ordering Information
table. Remove Pentium reference on page
1286064 AESA

See ECN Change status to final
2750166 TSAI
08/10/09 Post to external web
2761988 CXQ
09/10/09 Fixed Ordering Infomation table replacement error of “lead” with “Pb”.
2894960 KVM
03/18/10
Removed following obsolete parts from the ordering information table CY7B991-7LMB, CY7B992-7LMB, CY7B992-5JI, CY7B992-5JIT Updated package diagram Updated sales links Added Table of Contents

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

All trademarks or registered trademarks referenced herein are property of the respective corporations.

Page 20 of 20
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Datasheet ID: CY7B992-7JXCT 507840