CY7B952-SXCT

CY7B952-SXCT Datasheet

CY7B952

Part	Datasheet
CY7B952-SXCT	CY7B952-SXCT (pdf)

Related Parts	Information
CY7B952-SXC	CY7B952-SXC

PDF Datasheet Preview
CY7B952 SST SONET/SDH Serial Transceiver SST SONET/SDH Serial Transceiver • OC-3 Compliant with Bellcore and CCITT ITU specifications on Jitter Generation UI Jitter Transfer <130 kHz Jitter Tolerance • SONET/SDH and ATM Compliant • Compatible with IGT WAC013, IGT WAC413, and PMC-Sierra PM5343 • Clock and data recovery from or 155.52-MHz datastream • 155.52-MHz clock multiplication from 19.44-MHz source • 51.84-MHz clock multiplication from 6.48-MHz source • 1% frequency agility • Line Receiver Inputs No external buffering required • Differential output buffering • 100K ECL compatible I/O • No output clock “drift” without data transitions • Link Status Indication • Loop-back testing • Single +5 V supply • 24-pin SOIC • Compatible with fiber-optic modules, coaxial cable, and twisted pair media • Power-down options to minimize power or crosstalk • Low operating current <70 mA • BiCMOS Functional Description The SONET/SDH Serial Transceiver SST is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system. Logic Block Diagram LOOP t MODE FC+ RIN+ RECEIVE TRANSMIT RCLK+ RSER+ LFI t TOUT+ TSER+ TCLK+ REFCLK+ • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY7B952 Contents Pin Configuration 3 SONET/SDH Overhead Processing Application 3 Pin Descriptions 4 Description 5 Operating Frequency 5 Transmit Functions 5 Receive Functions 5 Carrier Detect CD and Link Fault Indicator LFI Functions 5 Loop Back Testing 6 SONET-compliant Testing 6 Power Down Modes 6 Applications 6 Maximum Ratings 7 Operating Range 7 Electrical Characteristics 7 Capacitance 9 AC Test Loads and Waveforms 9 Switching Characteristics 10 Switching Waveforms for the CY7B952 SONET/SDH Serial Transceiver 11 Ordering Information 12 Ordering Code Definitions 12 Package Diagram 13 Acronyms 14 Document Conventions 14 Units of Measure 14 Document History Page 15 Sales, Solutions, and Legal Information 16 Worldwide Sales and Design Support 16 Products 16 PSoC Solutions 16 Page 2 of 16 [+] Feedback Pin Configuration Figure 24-pin SOIC Top View RIN+ MODE VCC CD LOOP REFCLK+ TOUT+ 6 CY7B952 19 RCLK+ RSER+ LFI VCC VSS VCC TCLK+ TSER+ SONET/SDH Overhead Processing Application Clock/Data Recovery Line Driver Cypress CY7B952 S->P->S SONET/SDH Transport Overhead Transceiver PMC-Sierra PM5343STXC SONET/SDH Path Overhead Transceiver PMC-Sierra PM5344SPTX CY7B952 Page 3 of 16 [+] Feedback CY7B952 Pin Descriptions Name RIN FC RSER RCLK CD TSER TOUT REFCLK TCLK LOOP Differential In Receive Input. This line receiver port connects the receive differential serial input data stream to the internal Receive PLL. This PLL will recover the embedded clock RCLK and data RSER information for one of two data rates depending on the state of the MODE pin. These inputs can receive very low amplitude signals and are compatible with all PECL signalling levels. If the RIN inputs are not being used, connect RIN+ to VCC and to VSS. Passive Passive Filter Capacitor Connection. These pins are used to connect the external loop damping capacitor and resistor for the internal clock and data recovery phase locked loop. A 301K and a non-polar 1  10% chip capacitor should be used in parallel for this connection. ECL Out Recovered Serial Data. These ECL 100K outputs +5 V referenced represent the recovered data from the input data stream RIN . This recovered data is aligned with the recovered clock RCLK with a sampling window compatible with most data processing devices. ECL Out Recovered Clock. These ECL 100K outputs +5 V referenced represent the recovered clock from the input data stream RIN . This recovered clock is used to sample the recovered data RSER and has timing compatible with most data processing devices. If both the RSER and the RCLK are tied to VCC or left unconnected, the entire Receive PLL will be powered down. TTL/ECL In Carrier Detect. This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output from optical modules or from external transition detection circuitry. When this input is at an ECL HIGH, the input data stream RIN is recovered normally by the Receive PLL. When this input is at an ECL LOW, the Receive PLL no longer aligns to RIN, but instead aligns with the REFCLK 8 frequency. Also, the Link Fault Indicator LFI will transition LOW, and the recovered data outputs RSER will remain LOW regardless of the signal level on the Receive data-stream inputs RIN . When the CD input is at a TTL LOW, the internal transitions detection circuitry is disabled. TTL Out Link Fault Indicator. This output indicates the status of the input data stream RIN . It is controlled by three functions the Carrier Detect CD input, the internal Transition Detector, and the Out of Lock OOL detector. The Transition Detector determines if RIN contains enough transitions to be accurately recovered by the Receive PLL. The Out of Lock detector determines if RIN is within the frequency range of the Receive PLL. When CD is HIGH and RIN has sufficient transitions and is within the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at an ECL LOW or RIN does not contain sufficient transitions or RIN is outside the frequency range of the Receive PLL then the LFI output will be LOW. If CD is at a TTL LOW then the LFI output will only transition LOW when the frequency of RIN is outside the range of the Receive PLL. Ordering Information Speed ns Ordering Code 25 CY7B952-SXC CY7B952-SXCT Ordering Code Definitions Package Name Package Type S13 24-pin 300-Mil Molded SOIC S13 24-pin 300-Mil Molded SOIC CY 7B 952 - S X C X Operating Range Commercial X = blank or T blank = Tube T = Tape and Reel Temperature Range C = Commercial Pb-free Package Type S = 24-pin SOIC Base part number 952 = Serial Transceiver Marketing Code 7B = HOTLink Transceiver/Receiver Company ID CY = Cypress Page 12 of 16 [+] Feedback CY7B952 Package Diagram Figure 24-pin SOIC x Inches Package Outline, 51-85025 51-85025 *E Page 13 of 16 [+] Feedback Acronyms Acronym alternating current carrier detect direct current emitter coupled logic input/output link fault indicator printed circuit board PECL positive emitter coupled logic phase locked loop SOIC small-outline integrated circuit transistor-transistor logic voltage controlled oscillator CY7B952 Document Conventions Units of Measure Symbol dB °C kHz MHz µA µF mA mV ns % pF ppm V Unit of Measure decibel degree Celsius kilohertz megahertz microampere microfarad milliampere millivolt nanosecond ohm percent picofarad parts per million volt Page 14 of 16 [+] Feedback CY7B952 Document History Page Document Title CY7B952, SST SONET/SDH Serial Transceiver Document Number 38-02018 SAAC Ordering Information update. Added Ordering Code Definitions. 3434099 11/09/2011 SAAC Updated Package Diagram. Added Acronyms and Units of Measure. Updated in new template. Page 15 of 16 [+] Feedback CY7B952 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 16 of 16 SUNI is a trademark of PMC-Sierra, Incorporated. SST is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY7B952

SST SONET/SDH Serial Transceiver

SST SONET/SDH Serial Transceiver
• OC-3 Compliant with Bellcore and CCITT ITU specifications on Jitter Generation UI Jitter Transfer <130 kHz Jitter Tolerance
• SONET/SDH and ATM Compliant
• Compatible with IGT WAC013, IGT WAC413, and PMC-Sierra

PM5343
• Clock and data recovery from or 155.52-MHz
datastream
• 155.52-MHz clock multiplication from 19.44-MHz source
• 51.84-MHz clock multiplication from 6.48-MHz source
• 1% frequency agility
• Line Receiver Inputs No external buffering required
• Differential output buffering
• 100K ECL compatible I/O
• No output clock “drift” without data transitions
• Link Status Indication
• Loop-back testing
• Single +5 V supply
• 24-pin SOIC
• Compatible with fiber-optic modules, coaxial cable, and twisted
pair media
• Power-down options to minimize power or crosstalk
• Low operating current <70 mA
• BiCMOS

Functional Description

The SONET/SDH Serial Transceiver SST is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

Logic Block Diagram

LOOP t

MODE

FC+ RIN+

RECEIVE TRANSMIT

RCLK+ RSER+

LFI t

TOUT+

TSER+

TCLK+

REFCLK+
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY7B952

Contents

Pin Configuration 3 SONET/SDH Overhead Processing Application 3 Pin Descriptions 4 Description 5

Operating Frequency 5 Transmit Functions 5 Receive Functions 5 Carrier Detect CD and Link Fault Indicator LFI Functions 5 Loop Back Testing 6 SONET-compliant Testing 6 Power Down Modes 6 Applications 6 Maximum Ratings 7 Operating Range 7 Electrical Characteristics 7 Capacitance 9
AC Test Loads and Waveforms 9 Switching Characteristics 10 Switching Waveforms for the CY7B952 SONET/SDH Serial Transceiver 11 Ordering Information 12
Ordering Code Definitions 12 Package Diagram 13 Acronyms 14 Document Conventions 14

Units of Measure 14 Document History Page 15 Sales, Solutions, and Legal Information 16

Worldwide Sales and Design Support 16 Products 16 PSoC Solutions 16

Page 2 of 16 [+] Feedback

Pin Configuration

Figure 24-pin SOIC Top View

RIN+ MODE

VCC CD LOOP REFCLK+ TOUT+
6 CY7B952 19

RCLK+

RSER+ LFI

VCC VSS VCC TCLK+ TSER+

SONET/SDH Overhead Processing Application

Clock/Data Recovery

Line Driver Cypress CY7B952

S->P->S

SONET/SDH

Transport Overhead Transceiver

PMC-Sierra PM5343STXC

SONET/SDH Path

Overhead Transceiver

PMC-Sierra PM5344SPTX

CY7B952

Page 3 of 16 [+] Feedback

CY7B952

Pin Descriptions

Name RIN FC RSER RCLK CD

TSER TOUT REFCLK

TCLK LOOP

Differential In Receive Input. This line receiver port connects the receive differential serial input data stream to the internal Receive PLL. This PLL will recover the embedded clock RCLK and data RSER information for one of two data rates depending on the state of the MODE pin. These inputs can receive very low
amplitude signals and are compatible with all PECL signalling levels. If the RIN inputs are not being used, connect RIN+ to VCC and to VSS.

Passive

Passive Filter Capacitor Connection. These pins are used to connect the external loop damping capacitor and resistor for the internal clock and data recovery phase locked loop. A 301K and a non-polar 1  10% chip capacitor should be used in parallel for this connection.

ECL Out

Recovered Serial Data. These ECL 100K outputs +5 V referenced represent the recovered data from the input data stream RIN . This recovered data is aligned with the recovered clock RCLK with a sampling window compatible with most data processing devices.

ECL Out

Recovered Clock. These ECL 100K outputs +5 V referenced represent the recovered clock from the input data stream RIN . This recovered clock is used to sample the recovered data RSER and has timing compatible with most data processing devices. If both the RSER and the RCLK are tied to VCC or left unconnected, the entire Receive PLL will be powered down.

TTL/ECL In

Carrier Detect. This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output from optical modules or from external transition detection circuitry. When this input is at an ECL HIGH, the input data stream RIN is recovered normally by the Receive PLL. When this input is at an ECL LOW, the Receive PLL no longer aligns to RIN, but instead aligns with the REFCLK 8 frequency. Also, the Link Fault Indicator LFI will transition LOW, and the recovered data outputs RSER will remain LOW regardless of the signal level on the Receive data-stream inputs RIN . When the CD input is at a TTL LOW, the internal transitions detection circuitry is disabled.

TTL Out

Link Fault Indicator. This output indicates the status of the input data stream RIN . It is controlled by three functions the Carrier Detect CD input, the internal Transition Detector, and the Out of Lock OOL detector. The Transition Detector determines if RIN contains enough transitions to be accurately recovered by the Receive PLL. The Out of Lock detector determines if RIN is within the frequency range of the Receive PLL. When CD is HIGH and RIN has sufficient transitions and is within the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at an ECL LOW or RIN does not contain sufficient transitions or RIN is outside the frequency range of the Receive PLL then the LFI output will be LOW. If CD is at a TTL LOW then the LFI output will only transition LOW when the frequency of RIN is outside the range of the Receive PLL.
Ordering Information

Speed ns
Ordering Code
25 CY7B952-SXC

CY7B952-SXCT
Ordering Code Definitions

Package Name

Package Type

S13 24-pin 300-Mil Molded SOIC

S13 24-pin 300-Mil Molded SOIC

CY 7B 952 - S X C X

Operating Range

Commercial

X = blank or T blank = Tube T = Tape and Reel Temperature Range C = Commercial Pb-free Package Type S = 24-pin SOIC Base part number 952 = Serial Transceiver Marketing Code 7B = HOTLink Transceiver/Receiver Company ID CY = Cypress

Page 12 of 16 [+] Feedback

CY7B952

Package Diagram

Figure 24-pin SOIC x Inches Package Outline, 51-85025
51-85025 *E

Page 13 of 16 [+] Feedback

Acronyms

Acronym
alternating current
carrier detect
direct current
emitter coupled logic
input/output
link fault indicator
printed circuit board

PECL
positive emitter coupled logic
phase locked loop

SOIC
small-outline integrated circuit
transistor-transistor logic
voltage controlled oscillator

CY7B952

Document Conventions

Units of Measure

Symbol dB °C kHz MHz µA µF mA mV ns
% pF ppm V

Unit of Measure decibel degree Celsius kilohertz megahertz microampere microfarad milliampere millivolt nanosecond ohm percent picofarad parts per million volt

Page 14 of 16 [+] Feedback

CY7B952

Document History Page

Document Title CY7B952, SST SONET/SDH Serial Transceiver Document Number 38-02018
SAAC Ordering Information update.
Added Ordering Code Definitions.
3434099 11/09/2011 SAAC Updated Package Diagram.

Added Acronyms and Units of Measure.

Updated in new template.

Page 15 of 16 [+] Feedback

CY7B952

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB
cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 16 of 16

SUNI is a trademark of PMC-Sierra, Incorporated. SST is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7B952-SXCT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7B952-SXCT 507836