CY6264-70SNC

CY6264-70SNC Datasheet

CY6264

Part	Datasheet
CY6264-70SNC	CY6264-70SNC (pdf)

PDF Datasheet Preview
CY6264 8K x 8 Static RAM • 55, 70 ns access times • CMOS for optimum speed/power • Easy memory expansion with CE1, CE2, and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected Functional Description The CY6264 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable CE1 , an active HIGH chip enable CE2 , and active LOW output enable OE and three-state drivers. Both devices have an automatic power-down feature CE1 , reducing the power consumption by over 70% when deselected. The CY6264 is packaged in a 450-mil 300-mil body SOIC. An active LOW write enable signal WE controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins I/O0 through I/O7 is written into the memory location addressed by the address present on the address pins A0 through A12 . Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable WE is HIGH. A die coat is used to insure alpha immunity. Logic Block Diagram A1 A2 A3 A4 A5 A6 A7 A8 CE1 CE2 WE OE INPUT BUFFER 256 x 32 x 8 ARRAY POWER COLUMN DECODER DOWN I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Pin Configuration SOIC Top View A7 5 A8 6 A9 7 A10 8 A11 9 A12 10 I/O0 11 I/O1 12 I/O2 13 GND 14 28 VCC 27 WE 26 CE2 25 A3 24 A2 23 A1 22 OE 21 A0 20 CE1 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 ROW DECODER A0 A9 A10 A11 A12 SENSE AMPS Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 [+] Feedback CY6264 Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current Shaded areas contain advance information. Commercial Industrial Commercial Industrial CY6264-55 CY6264-70 Unit 20/15 20/15 Maximum Ratings Above which the useful life may be impaired. For user guidelines, not tested. Storage Temperature to +150°C Ambient Temperature with Power to +125°C Supply Voltage to Ground Potential to +7.0V DC Voltage Applied to Outputs in High Z State[1] to +7.0V DC Input to +7.0V Ordering Information Speed ns Ordering Code CY6264-55SC CY6264-70SC CY6264-55SNC CY6264-55SNXC CY6264-70SNC CY6264-70SNXC CY6264-70SNI CY6264-70SNXI Shaded areas contain advance information. Package Name S28.33 S28.33 SN28 Package Type 28-Lead 330-Mil SOIC[13] 28-Lead 330-Mil SOIC[13] 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC Pb-free 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC Pb-free 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC Pb-free CY6264 Operating Range Commercial Industrial Package Diagrams 28-lead 300 mil SNC Package Outline Narrow Body SN28 PIN 1 ID DIMENSIONS IN INCHES OMEDATA CSPI MIN. MAX. Note Not recommended for new dAesigns. TYP. DETAIL "A" SEATING PLANE DETAIL "B" 51-85092-B Page 8 of 10 [+] Feedback Package Diagrams continued 28-Lead SOIC with Wide Body S28.33 CURRENT SOIC WITH WIDE BODY PIN 1 ID DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 0.79gms PART # S28.33 STANDARD PKG. SZ28.33 LEAD FREE PKG. CY6264 MIN. MAX. TYP. SEATING PLANE 51-85058-B Page 9 of 10 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

PDF Datasheet Preview

CY6264
8K x 8 Static RAM
• 55, 70 ns access times
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2, and OE
features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected

Functional Description

The CY6264 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable CE1 , an active HIGH chip enable CE2 , and active LOW output enable OE and three-state drivers. Both devices have an automatic
power-down feature CE1 , reducing the power consumption by over 70% when deselected. The CY6264 is packaged in a 450-mil 300-mil body SOIC.

An active LOW write enable signal WE controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins I/O0 through I/O7 is written into the memory location addressed by the address present on the address pins A0 through A12 . Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins is present on the eight data input/output pins.

The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable WE is HIGH. A die coat is used to insure alpha immunity.

Logic Block Diagram

A1 A2 A3 A4 A5 A6 A7 A8

CE1 CE2 WE OE

INPUT BUFFER
256 x 32 x 8 ARRAY

POWER

COLUMN DECODER DOWN

I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

Pin Configuration

SOIC Top View

A7 5 A8 6 A9 7 A10 8 A11 9 A12 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC
27 WE
26 CE2
25 A3
24 A2 23 A1 22 OE 21 A0 20 CE1 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3

ROW DECODER A0 A9 A10 A11 A12

SENSE AMPS

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600
[+] Feedback

CY6264

Selection Guide

Maximum Access Time Maximum Operating Current Maximum Standby Current

Shaded areas contain advance information.

Commercial Industrial Commercial Industrial

CY6264-55

CY6264-70

Unit
20/15
20/15

Maximum Ratings

Above which the useful life may be impaired. For user guidelines, not tested. Storage Temperature to +150°C Ambient Temperature with Power to +125°C Supply Voltage to Ground Potential to +7.0V DC Voltage Applied to Outputs in High Z State[1] to +7.0V DC Input to +7.0V
Ordering Information

Speed ns
Ordering Code

CY6264-55SC

CY6264-70SC

CY6264-55SNC

CY6264-55SNXC

CY6264-70SNC

CY6264-70SNXC

CY6264-70SNI

CY6264-70SNXI

Shaded areas contain advance information.

Package Name S28.33 S28.33 SN28

Package Type 28-Lead 330-Mil SOIC[13] 28-Lead 330-Mil SOIC[13] 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC Pb-free 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC Pb-free 28-Lead 300-Mil SOIC 28-Lead 300-Mil SOIC Pb-free

CY6264

Operating Range

Commercial Industrial

Package Diagrams
28-lead 300 mil SNC Package Outline Narrow Body SN28

PIN 1 ID

DIMENSIONS IN INCHES

OMEDATA

CSPI

MIN. MAX.

Note Not recommended for new dAesigns. TYP.

DETAIL "A"

SEATING PLANE

DETAIL "B"
51-85092-*B

Page 8 of 10 [+] Feedback

Package Diagrams continued
28-Lead SOIC with Wide Body S28.33 CURRENT SOIC WITH WIDE BODY

PIN 1 ID

DIMENSIONS IN INCHES[MM] PACKAGE WEIGHT 0.79gms

PART # S28.33 STANDARD PKG. SZ28.33 LEAD FREE PKG.

CY6264

MIN. MAX.

TYP.

SEATING PLANE
51-85058-*B

Page 9 of 10

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY6264-70SNC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY6264-70SNC 507832