CY62167DV18LL-55BVXIT

CY62167DV18LL-55BVXIT Datasheet

CY62167DV18

Part	Datasheet
CY62167DV18LL-55BVXIT	CY62167DV18LL-55BVXIT (pdf)

Related Parts	Information
CY62167DV18LL-55BVXI	CY62167DV18LL-55BVXI

PDF Datasheet Preview
CY62167DV18 16-Mbit 1M x 16 Static RAM • Very high speed 55 ns • Wide voltage range • Ultra low active power Typical active current mA f = 1 MHz Typical active current 15 mA f = fmax • Ultra low standby power • Easy memory expansion with CE1, CE2, and OE features • Automatic power down when deselected • CMOS for optimum speed and power • Available in Pb-free 48-ball VFBGA package Functional Description[1] The CY62167DV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99% when addresses are not toggling. Placing the device into standby mode reduces power Logic Block Diagram consumption by more than 99% when deselected CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH . The input and output pins IO0 through IO15 are placed in a high impedance state when: • Deselected CE1 HIGH or CE2 LOW • Outputs are disabled OE HIGH • Both Byte High Enable BHE and Byte Low Enable BLE are disabled BHE, BLE HIGH • Write operation is active CE1 LOW, CE2 HIGH and WE LOW To write to the device, take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW. If BLE is LOW, then data from IO pins IO0 through IO7 is written into the location specified on the address pins A0 through A19 . If BHE is LOW then data from IO pins IO8 through IO15 is written into the location specified on the address pins A0 through A19 . To read from the device, take Chip Enables CE1 LOW and CE2 HIGH and OE LOW while forcing the WE HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If BHE is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes. ROW DECODER A11 A12 A13 A14 A15 A16 AA1187 A19 SENSE AMPS DATA IN DRIVERS A8 A7 1M x 16 RAM Array Power Down Circuit COLUMN DECODER BYTE CE1 OE Note For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY62167DV18 Product Portfolio Product CY62167DV18LL VCC Range V Typ[2] Speed ns Power Dissipation Operating ICC mA f = 1MHz Typ[2] Max f = fmax Typ[2] Max Standby ISB2 µA Typ[2] Pin Configuration [3] 48-Ball VFBGA Top View 1 2 34 56 BLE OE A0 A1 A2 CE2 A Ordering Information Speed ns Ordering Code CY62167DV18LL-55BVXI Package Diagram Package Type 51-85178 48-ball Fine Pitch BGA 8 x 1 mm Pb-free Operating Range Industrial Page 9 of 11 [+] Feedback CY62167DV18 Package Diagrams Figure 48-Ball VFBGA 8 x 1 mm , 51-85178 TOP VIEW A1 CORNER 12 3 4 5 6 BOTTOM VIEW M C M C A B Ø0.30±0.05 48X A1 CORNER 6 54 3 2 1 B 0.15 4X C MAX. MAX. SEATING PLANE C 51-85178-** MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Page 10 of 11 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY62167DV18 Document History Page Document Title CY62167DV18 16-Mbit 1M x 16 Static RAM Document Number 38-05326 ECN NO. Issue Date Orig. of Change Description of Change 118406 09/30/02 GUG New Data Sheet 123690 02/11/03 DPM Changed Advance to Preliminary Added package diagram 126554 04/25/03 DPM Minor Change Changed sunset owner from DPM to HRT 1015643 See ECN VKN Converted from preliminary to final Removed “L” parts Removed 70 ns speed bin Updated footnote #3 Updated Ordering Information table Page 11 of 11 [+] Feedback

PDF Datasheet Preview

CY62167DV18
16-Mbit 1M x 16 Static RAM
• Very high speed 55 ns
• Wide voltage range
• Ultra low active power

Typical active current mA f = 1 MHz Typical active current 15 mA f = fmax
• Ultra low standby power
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package

Functional Description[1]

The CY62167DV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99% when addresses are not toggling. Placing the device into standby mode reduces power

Logic Block Diagram
consumption by more than 99% when deselected CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH . The input and output pins IO0 through IO15 are placed in a high impedance state when:
• Deselected CE1 HIGH or CE2 LOW
• Outputs are disabled OE HIGH
• Both Byte High Enable BHE and Byte Low Enable BLE are disabled BHE, BLE HIGH
• Write operation is active CE1 LOW, CE2 HIGH and WE LOW

To write to the device, take Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW. If BLE is LOW, then data from IO pins IO0 through IO7 is written into the location specified on the address pins A0 through A19 . If BHE is LOW then data from IO pins IO8 through IO15 is written into the location specified on the address pins A0 through A19 . To read from the device, take Chip Enables CE1 LOW and CE2 HIGH and OE LOW while forcing the WE HIGH. If BLE is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If BHE is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes.

ROW DECODER A11 A12 A13 A14 A15 A16 AA1187 A19

SENSE AMPS

DATA IN DRIVERS

A8 A7
1M x 16

RAM Array

Power Down Circuit

COLUMN DECODER

BYTE

CE1 OE

Note For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY62167DV18

Product Portfolio

Product CY62167DV18LL

VCC Range V

Typ[2]

Speed ns

Power Dissipation

Operating ICC mA
f = 1MHz Typ[2] Max
f = fmax Typ[2] Max

Standby ISB2 µA

Typ[2]

Pin Configuration [3]
48-Ball VFBGA Top View
1 2 34 56

BLE OE A0 A1 A2 CE2 A
Ordering Information

Speed ns
Ordering Code CY62167DV18LL-55BVXI

Package Diagram

Package Type
51-85178 48-ball Fine Pitch BGA 8 x 1 mm Pb-free

Operating Range

Industrial

Page 9 of 11 [+] Feedback

CY62167DV18

Package Diagrams

Figure 48-Ball VFBGA 8 x 1 mm , 51-85178

TOP VIEW

A1 CORNER 12 3 4 5 6

BOTTOM VIEW

M C M C A B Ø0.30±0.05 48X

A1 CORNER
6 54 3 2 1

B 0.15 4X

C MAX.

MAX.

SEATING PLANE C
51-85178-**

MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 10 of 11

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY62167DV18

Document History Page

Document Title CY62167DV18 16-Mbit 1M x 16 Static RAM Document Number 38-05326

ECN NO. Issue Date

Orig. of Change

Description of Change
118406 09/30/02 GUG New Data Sheet
123690 02/11/03 DPM Changed Advance to Preliminary

Added package diagram
126554 04/25/03 DPM Minor Change Changed sunset owner from DPM to HRT
1015643 See ECN VKN Converted from preliminary to final

Removed “L” parts

Removed 70 ns speed bin

Updated footnote #3
Updated Ordering Information table

Page 11 of 11 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62167DV18LL-55BVXIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY62167DV18LL-55BVXIT 507823