CY62157DV30L-55ZSXET

CY62157DV30L-55ZSXET Datasheet

CY62157DV30

Part	Datasheet
CY62157DV30L-55ZSXET	CY62157DV30L-55ZSXET (pdf)

Related Parts	Information
CY62157DV30LL-55ZSXI	CY62157DV30LL-55ZSXI
CY62157DV30LL-55BVXI	CY62157DV30LL-55BVXI
CY62157DV30L-55BVXET	CY62157DV30L-55BVXET
CY62157DV30L-55ZSXE	CY62157DV30L-55ZSXE
CY62157DV30LL-55BVXA	CY62157DV30LL-55BVXA
CY62157DV30LL-55BVXAT	CY62157DV30LL-55BVXAT
CY62157DV30L-55BVXE	CY62157DV30L-55BVXE

PDF Datasheet Preview
CY62157DV30 8-Mbit 512K x 16 Static RAM • Temperature Ranges Industrial to 85°C Automotive-A to 85°C Automotive-E to 125°C • Very high speed 45 ns • Wide voltage range • Pin-compatible with CY62157CV25, CY62157CV30, and CY62157CV33 • Ultra-low active power Typical active current mA f = 1 MHz Typical active current 12 mA f = fmax • Ultra-low standby power • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Available in Pb-free and non Pb-free 48-ball FBGA, 44-pin TSOPII, and Pb-free 48-pin TSOPI Logic Block Diagram A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DATA-IN DRIVERS 512K x 16 RAM Array COLUMN DECODER Power-down Circuit ROW DECODER A11 A12 A13 A14 A15 A16 AA1187 SENSE AMPS Functional Description[1] The CY62157DV30 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE1HIGH or CE2 LOW , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH , or during a write operation CE1 LOW, CE2 HIGH and WE LOW . Writing to the device is accomplished by taking Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A18 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A18 . Reading from the device is accomplished by taking Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes. BHE WE OE BLE CE2 CE1 Note For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY62157DV30 Product Portfolio Product Range CY62157DV30L Industrial CY62157DV30LL Industrial CY62157DV30LL Automotive-A CY62157DV30L Automotive-E Pin Configuration[4, 5, 6] Power Dissipation VCC Range V Min. Typ.[2] Max. Speed ns Operating ICC, mA f = 1MHz f = fmax Typ.[2] Max. Typ.[2] Max. Standby ISB2, µA Ordering Information Speed ns 45 55 Ordering Code CY62157DV30L-45BVI CY62157DV30LL-45ZSXI CY62157DV30LL-55BVI CY62157DV30L-55BVXI CY62157DV30LL-55BVXI CY62157DV30L-55ZXI CY62157DV30LL-55ZSI CY62157DV30L-55ZSXI CY62157DV30LL-55ZSXI CY62157DV30LL-55BVXA CY62157DV30L-55BVXE CY62157DV30L-55ZSXE CY62157DV30LL-70BVI CY62157DV30LL-70BVXI Package Diagram 51-85150 51-85087 51-85150 Package Type 48-ball 6 x 8 x 1 mm FBGA 44-pin TSOP II Pb-free 48-ball 6 x 8 x 1 mm FBGA 48-ball 6 x 8 x 1 mm FBGA Pb-free 51-85183 44-pin TSOP I Pb-free 51-85087 44-pin TSOP II 44-pin TSOP II Pb-free 51-85150 51-85150 51-85087 51-85150 48-ball 6 x 8 x 1 mm FBGA Pb-free 48-ball 6 x 8 x 1 mm FBGA Pb-free 44-pin TSOP II Pb-free 48-ball 6 x 8 x 1 mm FBGA 48-ball 6 x 8 x 1 mm FBGA Pb-free Operating Range Industrial Automotive-A Automotive-E Industrial Package Diagrams TOP VIEW 48-ball FBGA 6 x 8 x 1 mm 51-85150 A1 CORNER 12 3 4 5 6 BOTTOM VIEW A1 CORNER M C M C A B Ø0.30±0.05 48X 6 54 3 2 1 B 0.15 4X C MAX. SEATING PLANE C 51-85150-D MAX. Page 10 of 12 [+] Feedback CY62157DV30 Package Diagrams continued 48-pin TSOP I 12 mm x mm x mm 51-85183 DIMENSIONS IN INCHES[MM] MIN. JEDEC # MO-142 MAX. TYP. 0°-5° MAX. GAUGE PLANE 44-pin TSOP II 51-85087 SEATING PLANE 51-85183-A 51-85087-*A title and in the Ordering Information table Added footnotes 4, 5 and 11 Modified footnote 8 to include ramp time and wait time Removed MAX value for VDR on Data Retention Characteristics table Changed ordering code for Pb-free parts Modified voltage limits in Maximum Ratings section 236628 See ECN SYT/AJU Added 45-ns and 70-ns Speed Bins Added Automotive product information 257349 See ECN PCI Added test condition for 45 ns part footnote #13 on page 4 372074 See ECN SYT Added Pb-Free Automotive Part in the Ordering Information Removed ‘Preliminary’ tag from Automotive Information 433838 See ECN ZSD Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Updated the thermal resistance table Updated the ordering information table and changed the package name column to package diagram 488954 See ECN VKN Added Automotive-A product Updated ordering Information table Page 12 of 12 [+] Feedback

PDF Datasheet Preview

CY62157DV30
8-Mbit 512K x 16 Static RAM
• Temperature Ranges Industrial to 85°C Automotive-A to 85°C Automotive-E to 125°C
• Very high speed 45 ns
• Wide voltage range
• Pin-compatible with CY62157CV25, CY62157CV30, and

CY62157CV33
• Ultra-low active power

Typical active current mA f = 1 MHz Typical active current 12 mA f = fmax
• Ultra-low standby power
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball FBGA, 44-pin TSOPII, and Pb-free 48-pin TSOPI

Logic Block Diagram

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DATA-IN DRIVERS 512K x 16

RAM Array

COLUMN DECODER

Power-down Circuit

ROW DECODER A11 A12 A13 A14 A15 A16 AA1187

SENSE AMPS

Functional Description[1]

The CY62157DV30 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode when deselected CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE1HIGH or CE2 LOW , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH , or during a write operation CE1 LOW, CE2 HIGH and WE LOW .

Writing to the device is accomplished by taking Chip Enables CE1 LOW and CE2 HIGH and Write Enable WE input LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A18 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A18 .

Reading from the device is accomplished by taking Chip Enables CE1 LOW and CE2 HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes.

BHE WE

OE BLE

CE2 CE1

Note For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY62157DV30

Product Portfolio

Product

Range

CY62157DV30L Industrial

CY62157DV30LL Industrial

CY62157DV30LL Automotive-A

CY62157DV30L Automotive-E

Pin Configuration[4, 5, 6]

Power Dissipation

VCC Range V Min. Typ.[2] Max.

Speed ns

Operating ICC, mA
f = 1MHz
f = fmax

Typ.[2] Max. Typ.[2] Max.

Standby ISB2, µA
Ordering Information

Speed ns 45 55
Ordering Code

CY62157DV30L-45BVI CY62157DV30LL-45ZSXI CY62157DV30LL-55BVI CY62157DV30L-55BVXI CY62157DV30LL-55BVXI CY62157DV30L-55ZXI CY62157DV30LL-55ZSI CY62157DV30L-55ZSXI CY62157DV30LL-55ZSXI CY62157DV30LL-55BVXA CY62157DV30L-55BVXE CY62157DV30L-55ZSXE CY62157DV30LL-70BVI CY62157DV30LL-70BVXI

Package Diagram
51-85150
51-85087
51-85150

Package Type
48-ball 6 x 8 x 1 mm FBGA 44-pin TSOP II Pb-free 48-ball 6 x 8 x 1 mm FBGA 48-ball 6 x 8 x 1 mm FBGA Pb-free
51-85183 44-pin TSOP I Pb-free 51-85087 44-pin TSOP II
44-pin TSOP II Pb-free
51-85150 51-85150 51-85087 51-85150
48-ball 6 x 8 x 1 mm FBGA Pb-free 48-ball 6 x 8 x 1 mm FBGA Pb-free 44-pin TSOP II Pb-free 48-ball 6 x 8 x 1 mm FBGA 48-ball 6 x 8 x 1 mm FBGA Pb-free

Operating Range Industrial

Automotive-A Automotive-E

Industrial

Package Diagrams

TOP VIEW
48-ball FBGA 6 x 8 x 1 mm 51-85150

A1 CORNER 12 3 4 5 6

BOTTOM VIEW A1 CORNER

M C M C A B Ø0.30±0.05 48X
6 54 3 2 1

B 0.15 4X

C MAX.

SEATING PLANE C
51-85150-*D

MAX.

Page 10 of 12 [+] Feedback

CY62157DV30

Package Diagrams continued
48-pin TSOP I 12 mm x mm x mm 51-85183

DIMENSIONS IN INCHES[MM] MIN. JEDEC # MO-142

MAX.

TYP.
0°-5°

MAX.

GAUGE PLANE
44-pin TSOP II 51-85087

SEATING PLANE
51-85183-*A
51-85087-*A
title and in the Ordering Information table

Added footnotes 4, 5 and 11

Modified footnote 8 to include ramp time and wait time

Removed MAX value for VDR on Data Retention Characteristics table
Changed ordering code for Pb-free parts

Modified voltage limits in Maximum Ratings section
236628 See ECN SYT/AJU Added 45-ns and 70-ns Speed Bins

Added Automotive product information
257349 See ECN

PCI Added test condition for 45 ns part footnote #13 on page 4
372074 See ECN SYT Added Pb-Free Automotive Part in the Ordering Information

Removed ‘Preliminary’ tag from Automotive Information
433838 See ECN ZSD Changed the address of Cypress Semiconductor Corporation on Page #1
from “3901 North First Street” to “198 Champion Court”

Updated the thermal resistance table
Updated the ordering information table and changed the package name
column to package diagram
488954 See ECN VKN Added Automotive-A product
Updated ordering Information table

Page 12 of 12 [+] Feedback

More datasheets: B41041A7107M | B41041A7108M | B41041A7108T | B41041A7156M | B41041A7157M | B41041A6476M | CY62157DV30LL-55ZSXI | CY62157DV30LL-55BVXI | CY62157DV30L-55BVXET | CY62157DV30L-55ZSXE

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62157DV30L-55ZSXET Datasheet file may be downloaded here without warranties.

Datasheet ID: CY62157DV30L-55ZSXET 507822