CY62136VLL-70ZSXE

CY62136VLL-70ZSXE Datasheet

CY62136V

Part	Datasheet
CY62136VLL-70ZSXE	CY62136VLL-70ZSXE (pdf)

Related Parts	Information
CY62136VLL-70ZSXET	CY62136VLL-70ZSXET

PDF Datasheet Preview
CY62136V 2-Mbit 128K x 16 Static RAM • High speed 55 ns • Temperature Ranges Industrial to 85°C Automotive to 125°C • Wide voltage range 2.7V 3.6V • Ultra-low active, standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • CMOS for optimum speed/power • Available in a Pb-free and non Pb-free 44-pin TSOP Type II forward pinout and 48-ball FBGA packages Functional Description[1] The CY62136V is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected CE HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE LOW, and WE LOW . Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A16 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A16 . Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes. Logic Block Diagram DATA IN DRIVERS 128K x 16 RAM Array A2 A1 A0 I/O0 I/O7 I/O8 I/O15 ROW DECODER A11 A12 A13 A14 A15 A16 SENSE AMPS COLUMN DECODER BHE WE CE OE BLE Note For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY62136V Product Portfolio Product CY62136VLL VCC Range V Min. Typ.[2] Max. Power Dissipation Industrial Speed Grades Operating, ICC mA Standby, ISB2 µA Typ.[2] Maximum Typ.[2] Maximum Industrial Industrial Ordering Information Speed ns Ordering Code Package Diagram Package Type 55 CY62136VLL-55BAI 51-85096 48-ball Fine-Pitch Ball Grid Array 7 x 7 x mm CY62136VLL-55ZI CY62136VLL-55ZXI 70 CY62136VLL-70BAI CY62136VLL-70ZI CY62136VLL-70ZXI 51-85087 44-pin TSOP II 44-pin TSOP II Pb-free 51-85096 48-ball Fine-Pitch Ball Grid Array 7 x 7 x mm 51-85087 44-pin TSOP II 44-pin TSOP II Pb-free CY62136VLL-70ZSE 44-pin TSOP II CY62136VLL-70ZSXE 44-pin TSOP II Pb-free Please contact your local Cypress sales representative for availability of these parts Operating Range Industrial Industrial Automotive Package Diagrams 48-ball FBGA 7 x 7 x mm 51-85096 TOP VIEW PIN 1 CORNER LASER MARK 12 3 4 5 6 A B C D E F G H BOTTOM VIEW M C M C A B Ø0.30±0.05 48X 6 54321 PIN 1 CORNER A B C D E F G H B 0.15 4X SEATING PLANE C MAX. 51-85096-F Page 11 of 13 [+] Feedback Package Diagrams continued 44-pin TSOP II 51-85087 CY62136V 51-85087-A MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the products of their respective holders. Page 12 of 13 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be Replaced ‘Z’ with ‘ZS’ in the Ordering Code. 344595 See ECN SYT Added Lead-Free Package on page# 9 Changed Package Name from ZS44 to Z44 for the 44 TSOP II Package Replaced ‘ZS’ with ‘Z’ in the Ordering Code for Industrial 486789 See ECN VKN Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court”. Added FBGA Package for Industrial Operating range. Removed SL Power bin. Updated Ordering Information table. Page 13 of 13 [+] Feedback

PDF Datasheet Preview

CY62136V
2-Mbit 128K x 16 Static RAM
• High speed 55 ns
• Temperature Ranges Industrial to 85°C Automotive to 125°C
• Wide voltage range 2.7V 3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in a Pb-free and non Pb-free 44-pin TSOP

Type II forward pinout and 48-ball FBGA packages

Functional Description[1]

The CY62136V is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected CE HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , BHE and BLE are disabled BHE, BLE HIGH , or during a write operation CE LOW, and WE LOW .

Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A16 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A16 .

Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS
128K x 16

RAM Array

A2 A1 A0

I/O0 I/O7 I/O8 I/O15

ROW DECODER A11 A12 A13 A14 A15 A16

SENSE AMPS

COLUMN DECODER

BHE WE CE OE BLE

Note For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY62136V

Product Portfolio

Product CY62136VLL

VCC Range V

Min.

Typ.[2]

Max.

Power Dissipation Industrial

Speed

Grades

Operating, ICC mA

Standby, ISB2 µA

Typ.[2] Maximum Typ.[2]

Maximum

Industrial

Industrial
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type
55 CY62136VLL-55BAI
51-85096 48-ball Fine-Pitch Ball Grid Array 7 x 7 x mm

CY62136VLL-55ZI CY62136VLL-55ZXI 70 CY62136VLL-70BAI CY62136VLL-70ZI CY62136VLL-70ZXI
51-85087 44-pin TSOP II 44-pin TSOP II Pb-free
51-85096 48-ball Fine-Pitch Ball Grid Array 7 x 7 x mm 51-85087 44-pin TSOP II
44-pin TSOP II Pb-free

CY62136VLL-70ZSE
44-pin TSOP II

CY62136VLL-70ZSXE
44-pin TSOP II Pb-free

Please contact your local Cypress sales representative for availability of these parts

Operating Range Industrial

Industrial

Automotive

Package Diagrams
48-ball FBGA 7 x 7 x mm 51-85096

TOP VIEW

PIN 1 CORNER LASER MARK
12 3 4 5 6

A B C D E F G H

BOTTOM VIEW

M C M C A B Ø0.30±0.05 48X
6 54321

PIN 1 CORNER

A B C D E F G H

B 0.15 4X

SEATING PLANE C

MAX.
51-85096-*F

Page 11 of 13 [+] Feedback

Package Diagrams continued
44-pin TSOP II 51-85087

CY62136V
51-85087-*A

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the products of their respective holders.

Page 12 of 13

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
Replaced ‘Z’ with ‘ZS’ in the Ordering Code.
344595

See ECN

SYT Added Lead-Free Package on page# 9

Changed Package Name from ZS44 to Z44 for the 44 TSOP II Package
Replaced ‘ZS’ with ‘Z’ in the Ordering Code for Industrial
486789

See ECN

VKN Changed address of Cypress Semiconductor Corporation on Page# 1
from “3901 North First Street” to “198 Champion Court”.

Added FBGA Package for Industrial Operating range.

Removed SL Power bin.
Updated Ordering Information table.

Page 13 of 13 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62136VLL-70ZSXE Datasheet file may be downloaded here without warranties.

Datasheet ID: CY62136VLL-70ZSXE 507808