CY62128VLL-70ZC
CY62128VLL-70ZC Datasheet
1*CY62128V Family
| Part | Datasheet |
|---|---|
CY62128VLL-70ZC |
CY62128VLL-70ZC (pdf) |
| PDF Datasheet Preview |
|---|
| 1*CY62128V Family CY62128V Family • Low voltage range CY62128V CY62128V25 CY62128V18 • Low active power and standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • CMOS for optimum speed/power Functional Description The CY62128V family is composed of three high-performance CMOS static RAMs organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable CE1 , an active HIGH Chip Enable CE2 , an active 128K x 8 Static RAM LOW Output Enable OE and three-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. The CY62128V family is available in the standard 450-mil-wide SOIC, 32-lead TSOP-I, and STSOP packages. Writing to the device is accomplished by taking Chip Enable one CE1 and Write Enable WE inputs LOW and the Chip Enable two CE2 input HIGH. Data on the eight I/O pins I/O0 through I/O7 is then written into the location specified on the address pins A0 through A16 . Reading from the device is accomplished by taking Chip Enable one CE1 and Output Enable OE LOW while forcing Write Enable WE and Chip Enable two CE2 HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins I/O0 through I/O7 are placed in a high-impedance state when the device is deselected CE1 HIGH or CE2 LOW , the outputs are disabled OE HIGH , or during a write operation CE1 LOW, CE2 HIGH, and WE LOW . Logic Block Diagram A0 A1 A2 AA34 A5 A6 AA78 CE1 CE2 WE OE INPUT BUFFER 512x 256x 8 ARRAY COLUMN DECODER POWER DOWN I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 62128V-1 Pin Configurations Top View SOIC NC 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16 32 VCC 31 A15 30 CE2 29 WE 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE1 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 62128V-2 ROW DECODER A9 A10 A11 AA1123 A14 A15 A16 SENSE AMPS not to scale 17 A3 18 A2 19 A1 20 A0 21 I/O0 22 I/O1 23 I/O2 24 GND 25 I/O3 26 I/O4 27 I/O5 28 I/O6 29 I/O7 30 CE1 31 A10 32 OE 2267 WE 29 CE2 30 Ordering Information Speed ns Ordering Code 55 CY62128VLL-55ZAI 70 CY62128VL-70SC CY62128VLL-70SC CY62128VL-70ZC CY62128VLL-70ZC CY62128VL-70ZAC CY62128VLL-70ZAC CY62128VLL-70ZRC CY62128VLL-70SI CY62128VL-70ZI CY62128VLL-70ZI CY62128VL-70ZAI CY62128VLL-70ZAI CY62128VLL-70ZRI 200 CY62128V18L-200ZC CY62128V18L-200ZAI CY62128V18LL-200ZAI Document # 38-00547-*C Package Name ZA32 Package Type 32-Lead STSOP Type 1 32-Lead 450-Mil SOIC Z32 32-Lead TSOP Type 1 ZA32 32-Lead STSOP Type 1 ZR32 S34 Z32 ZA32 32-Lead STSOP Type 1 ZR32 Z32 ZA32 CY62128V Family Operating Range Industrial Commercial Industrial Commercial Industrial Package Diagrams CY62128V Family 32-Lead 450 MIL Molded SOIC S34 51-85081-A Package Diagrams CY62128V Family 32-Lead Thin Small Outline Package Z32 51-85056-C Package Diagrams |
| More datasheets: GLD140HG | 381 | DS-862GB-S6A1E | DS-862GB-U5A1E | DS-862GF-S6A1E | DS-862GF-U5A1E | DS-862GF-U2A1E | DS-862GB-U2A1E | CL-426F-AA-SD-TS | CL-426F-AACC-SD-TS |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62128VLL-70ZC Datasheet file may be downloaded here without warranties.