CY62127DV30L-55ZSXE

CY62127DV30L-55ZSXE Datasheet

CY62127DV30

Part	Datasheet
CY62127DV30L-55ZSXE	CY62127DV30L-55ZSXE (pdf)

Related Parts	Information
CY62127DV30LL-55BVXI	CY62127DV30LL-55BVXI
CY62127DV30LL-55ZXI	CY62127DV30LL-55ZXI
CY62127DV30LL-55ZXIT	CY62127DV30LL-55ZXIT
CY62127DV30L-55ZSXET	CY62127DV30L-55ZSXET
CY62127DV30L-55BVXET	CY62127DV30L-55BVXET
CY62127DV30L-55BVXE	CY62127DV30L-55BVXE
CY62127DV30LL-55BVXIT	CY62127DV30LL-55BVXIT

PDF Datasheet Preview
CY62127DV30 1-Mb 64K x 16 Static RAM • Temperature Ranges Industrial to 85°C Automotive to 125°C • Very high speed 45 ns • Wide voltage range 2.2V to 3.6V • Pin compatible with CY62127BV • Ultra-low active power Typical active current mA f = 1 MHz Typical active current 5 mA f = fMAX • Ultra-low standby power • Easy memory expansion with CE and OE features • Automatic power-down when deselected • Available in Pb-Free and non Pb-Free 48-ball FBGA and a 44-lead TSOP Type II packages Functional Description[1] The CY62127DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in Logic Block Diagram portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected CE HIGH or both BHE and BLE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH or during a write operation CE LOW and WE LOW . Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A15 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A15 . Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes DATA IN DRIVERS A10 10 A9 64K x 16 RAM Array 2048 x 512 A2 A1 A0 ROW DECODER A11 A12 A13 A14 A15 SENSE AMPS COLUMN DECODER Power -Down Circuit CE BHE BLE BHE WE CE OE BLE Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY62127DV30 Product Portfolio Product CY62127DV30L CY62127DV30LL CY62127DV30L VCC Range V Min. Typ. Max. Speed ns CY62127DV30LL CY62127DV30L 70 CY62127DV30LL Power Dissipation Operating, ICC mA f = 1 MHz Typ[4] Max. Typ.[4] f = fMAX Max. Ordering Information Speed ns Ordering Code Package Diagram Package Type 45 CY62127DV30LL-45BVXI 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm Pb-Free CY62127DV30LL-45ZXI 51-85087 44-lead TSOP Type II Pb-Free 55 CY62127DV30LL-55BVI 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm CY62127DV30LL-55BVXI 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm Pb-Free CY62127DV30LL-55ZI 51-85087 44-lead TSOP Type II CY62127DV30L-55ZXI 51-85087 44-lead TSOP Type II Pb-Free CY62127DV30LL-55ZXI 51-85087 44-lead TSOP Type II Pb-Free CY62127DV30L-55BVXE 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm Pb-Free CY62127DV30L-55ZSXE 51-85087 44-lead TSOP Type II Pb-Free 70 CY62127DV30L-70BVI 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm CY62127DV30LL-70BVXI 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm Pb-Free CY62127DV30L-70ZI 51-85087 44-lead TSOP Type II CY62127DV30LL-70ZXI 51-85087 44-lead TSOP Type II Pb-Free Please contact your local Cypress sales representative for availability of these parts Package Diagrams Operating Range Industrial Industrial Automotive Industrial 48-ball VFBGA 6 x 8 x 1 mm 51-85150 TOP VIEW A1 CORNER 12 3 4 5 6 A B C D E F G H BOTTOM VIEW A1 CORNER M C M C A B Ø0.30±0.05 48X 6 54 3 2 1 A B C D E F G H B 0.15 4X C MAX. Add 70-ns speed, updated ordering information 129000 08/29/03 CDY Changed Icc 1 MHz typ from mA to mA 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote # 8 on page #4 Added Lead-Free Package ordering information on page# 9 Changed 44-lead TSOP-II package name from Z44 to ZS44 346982 See ECN AJU Added 56-pin QFN package 369955 See ECN SYT Added Temperature Ranges in the Features Section on Page # 1 Added Automotive Specs for IIX,IOZ,ISB1and ISB2 in the Product portfolio on Page #2 and the DC Electrical Characteristics table on Page# 4 Added Automotive spec for ICCDR in the Data Retention Characteristics table on Page# 5 Added Pb-Free Automotive parts for 55 ns Speed bin 457685 See ECN NXR Removed 56-pin QFN package from product offering Updated ordering Information Table 470383 See ECN NXR Changed pin #23 of TSOP II from NC to DNU and updated footnote #2 Page 11 of 11 [+] Feedback

PDF Datasheet Preview

CY62127DV30
1-Mb 64K x 16 Static RAM
• Temperature Ranges Industrial to 85°C Automotive to 125°C
• Very high speed 45 ns
• Wide voltage range 2.2V to 3.6V
• Pin compatible with CY62127BV
• Ultra-low active power

Typical active current mA f = 1 MHz Typical active current 5 mA f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Available in Pb-Free and non Pb-Free 48-ball FBGA and a 44-lead TSOP Type II packages

Functional Description[1]

The CY62127DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in

Logic Block Diagram
portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected CE HIGH or both BHE and BLE are HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH or during a write operation CE LOW and WE LOW .

Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A15 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A15 .

Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes

DATA IN DRIVERS

A10 10 A9
64K x 16

RAM Array
2048 x 512

A2 A1 A0

ROW DECODER A11 A12 A13 A14 A15

SENSE AMPS

COLUMN DECODER

Power -Down Circuit

CE BHE BLE

BHE WE

CE OE BLE

Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY62127DV30

Product Portfolio

Product CY62127DV30L CY62127DV30LL CY62127DV30L

VCC Range V Min. Typ. Max.

Speed ns

CY62127DV30LL

CY62127DV30L 70

CY62127DV30LL

Power Dissipation

Operating, ICC mA
f = 1 MHz Typ[4] Max.

Typ.[4]
f = fMAX

Max.
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type
45 CY62127DV30LL-45BVXI 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm Pb-Free

CY62127DV30LL-45ZXI
51-85087 44-lead TSOP Type II Pb-Free
55 CY62127DV30LL-55BVI
51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm

CY62127DV30LL-55BVXI 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm Pb-Free

CY62127DV30LL-55ZI
51-85087 44-lead TSOP Type II

CY62127DV30L-55ZXI
51-85087 44-lead TSOP Type II Pb-Free

CY62127DV30LL-55ZXI
51-85087 44-lead TSOP Type II Pb-Free

CY62127DV30L-55BVXE 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm Pb-Free

CY62127DV30L-55ZSXE
51-85087 44-lead TSOP Type II Pb-Free
70 CY62127DV30L-70BVI
51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm

CY62127DV30LL-70BVXI 51-85150 48-ball Fine Pitch BGA 6 mm x 8 mm x 1 mm Pb-Free

CY62127DV30L-70ZI
51-85087 44-lead TSOP Type II

CY62127DV30LL-70ZXI
51-85087 44-lead TSOP Type II Pb-Free

Please contact your local Cypress sales representative for availability of these parts

Package Diagrams

Operating Range Industrial

Industrial

Automotive Industrial
48-ball VFBGA 6 x 8 x 1 mm 51-85150

TOP VIEW

A1 CORNER
12 3 4 5 6

A B C D E F G H

BOTTOM VIEW A1 CORNER

M C M C A B Ø0.30±0.05 48X
6 54 3 2 1

A B C D E F G H

B 0.15 4X

C MAX.
Add 70-ns speed, updated ordering information
129000 08/29/03 CDY Changed Icc 1 MHz typ from mA to mA
316039 See ECN
PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables

Added Footnote # 8 on page #4
Added Lead-Free Package ordering information on page# 9

Changed 44-lead TSOP-II package name from Z44 to ZS44
346982 See ECN AJU Added 56-pin QFN package
369955 See ECN SYT Added Temperature Ranges in the Features Section on Page # 1

Added Automotive Specs for IIX,IOZ,ISB1and ISB2 in the Product portfolio on Page #2 and the DC Electrical Characteristics table on Page# 4

Added Automotive spec for ICCDR in the Data Retention Characteristics table on Page# 5

Added Pb-Free Automotive parts for 55 ns Speed bin
457685 See ECN NXR Removed 56-pin QFN package from product offering
Updated ordering Information Table
470383 See ECN NXR Changed pin #23 of TSOP II from NC to DNU and updated footnote #2

Page 11 of 11 [+] Feedback

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Datasheet ID: CY62127DV30L-55ZSXE 507803